36.6.3 Block Diagram

Figure 36-25. Full-Duplex SPI Host Client Interconnection

When the SERCOM is configured for SPI operation, the SERCOM controls the direction and value of the I/O pins as given in the table below. Both PORT control bits, PINCFGn.PULLEN and PINCFGn.DRVSTR, are still effective. If the receiver is disabled, the data input pin can be used for other purposes. In Host mode, the client select line (SS) is hardware controlled when the Host Client Select Enable bit in the Control B register (CTRLB.MSSEN) is '1'.

In framed SPI mode (CTRLC.FRMEN = 1), the FSYNC direction is controlled by the frame type (host or client), set by the FMODE bit in the Control C register.

Table 36-8. SPI Pin Configuration
Pin	Host SPI	Client SPI
HOCI	Output	Input
HICO	Input	Output
SCK	Output	Input
SS / FSYNC	Output (CTRLB.MSSEN = 1) and (CTRLC.FRMEN = 0)	Input (CTRLC.FRMEN = 0)
	Output (CTRLC.FRMEN = 1) and (CTRLC.FMODE = 0)	Output (CTRLC.FRMEN = 1) and (CTRLC.FMODE = 0)
	Input (CTRLC.FRMEN = 1) and (CTRLC.FMODE = 1)	Input (CTRLC.FRMEN = 1) and (CTRLC.FMODE = 1)

The combined configuration of PORT, the Data In Pinout and the Data Out Pinout bit groups in the Control A register (CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals as given in the table above.