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PIC32CM SG00 Family Data Sheet
32-bit Arm® Cortex®-M23 MCU with Security, Functional Safety (FuSa), CAN-FD, Full-Speed USB, Enhanced Touch, and Advanced Analog
1 Guidelines for Getting Started
1.1 Basic Connection Requirements
1.2 Decoupling Capacitors
1.3 External Reset (RESET) Pin
1.4 Debugging or Programming Pins
1.5 JTAG
1.6 External Oscillator Pins
1.7 Unused I/Os
1.8 Considerations When Interfacing to Remotely Powered Circuits
1.9 Designing for High-Speed Peripherals
2 Configuration Summary
3 Ordering Information
4 Block Diagram
5 Pinout and Packaging
5.1 48-Pin TQFP and 48-Pin VQFN
5.2 64-Pin TQFP and 64-Pin VQFN
5.3 100-Pin TQFP
6 5V Tolerant Pins
7 Signal Description
8 Power Supplies and Startup Considerations
8.1 Power Domain Overview
8.2 Power Domain Constraints
8.3 Device Startup
8.4 Analog Peripherals Considerations
9 Product Mapping
10 Peripherals
10.1 Register Description
11 Processor and Architecture
11.1 Processor and Architecture
11.2 Arm Cortex-M23 Configuration
11.3 Nested Vector Interrupt Controller
11.4 NVIC Interrupt Mapping
11.5 High-Speed Bus
11.6 Bus Matrix Connectivity
12 Memories
12.1 Embedded Memories
12.2 Physical Memory Map
12.3 SRAM Memory Configuration
12.4 Flash Memories
12.5 Unique ID (UID)
13 PIC32CM SG00 Security Features
13.1 Data Flash
13.2 TrustRAM
13.3 Arm TrustZone for ARMv8-M
14 Implementation Defined Attribution Unit (IDAU)
14.1 Overview
14.2 IDAU Region Types
14.3 Main Region Types
14.4 Splittable Main Regions
14.5 H2PB Exempt Main Regions
14.6 SECNNONSEC_B Layout
14.7 IDAU Regions IDS
14.8 IDAU Regions Configuration
14.9 Configuration Write Lock
14.10 Linked IDAU Regions
14.11 Peripheral Dependencies
14.12 Register Summary
15 System Bus AHB - APB Bridge (H2PB)
15.1 Overview
15.2 Features
15.3 Functional Description
15.4 Peripheral Dependencies
15.5 Register Summary
16 Boot ROM
16.1 Boot ROM
16.2 Features
16.3 Block Diagram
16.4 Boot ROM Dependencies
16.5 Functional Description
16.6 Fuse Summary: ROMCFG
16.7 Fuse Summary: USERCFG
17 Multi-Channel RAM Controller (MCRAMC)
17.1 Overview
17.2 Features
17.3 Block Diagram
17.4 Functional Description
17.5 Peripheral Dependencies
17.6 Register Summary
18 Peripheral Access Controller (PAC)
18.1 Overview
18.2 Features
18.3 Block Diagram
18.4 Debug Operation
18.5 Register Access Protection
18.6 Functional Description
18.7 Peripheral Dependencies
18.8 Register Summary
19 Device Service Unit (DSU)
19.1 Overview
19.2 Features
19.3 Signal Description
19.4 DSU Block Diagram
19.5 Indexing
19.6 Debug Operation
19.7 Programming
19.8 Security Enforcement
19.9 Device Identification
19.10 Peripheral Dependencies
19.11 Register Summary
20 Clock Distribution System
20.1 Clock System
21 Oscillator Controller (OSCCTRL)
21.1 Overview
21.2 Features
21.3 OSCCTRL Block Diagram
21.4 Signal Descriptions
21.5 Functional Description
21.6 Product Dependencies
21.7 Peripheral Dependencies
21.8 Register Summary
22 Generic Clock Controller (GCLK)
22.1 Overview
22.2 Features
22.3 Block Diagram
22.4 Signal Description
22.5 Functional Description
22.6 Peripheral Dependencies
22.7 GCLK Peripheral Channel Control Mapping
22.8 Register Summary
23 Main Clock (MCLK)
23.1 Overview
23.2 Features
23.3 Block Diagram
23.4 Functional Description
23.5 Peripheral Dependencies
23.6 MCLK AHB/APB Clock Enable Peripheral Mapping
23.7 Register Summary
24 32 KHz Oscillators Controller (OSC32KCTRL)
24.1 Overview
24.2 Features
24.3 Block Diagram
24.4 Signal Description
24.5 Functional Description
24.6 Peripheral Dependencies
24.7 Register Summary
25 Watchdog Timer (WDT)
25.1 Overview
25.2 Features
25.3 Block Diagram
25.4 Functional Description
25.5 Peripheral Dependencies
25.6 Register Summary
26 Frequency Meter (FREQM)
26.1 Overview
26.2 Features
26.3 Block Diagram
26.4 Product Dependencies
26.5 Functional Description
26.6 Peripheral Dependencies
26.7 Register Summary
27 Real-Time Counter (RTC)
27.1 Overview
27.2 Features
27.3 Block Diagram
27.4 Signal Description
27.5 Peripheral Dependencies
27.6 Functional Description
27.7 Peripheral Dependencies
27.8 Register Summary - MODE0
27.9 Register Summary - MODE1
27.10 Register Summary - MODE2
27.11 Register Summary
28 Direct Memory Access Controller (DMAC)
28.1 Overview
28.2 Features
28.3 Block Diagram
28.4 Product Dependencies
28.5 Functional Description
28.6 Peripheral Dependencies
28.7 Register Summary
28 DMA Descriptor Register Summary
29 Supply Controller (SUPC)
29.1 Overview
29.2 Features
29.3 Block Diagram
29.4 Signals Description
29.5 Functional Description
29.6 Peripheral Dependencies
29.7 Register Summary
30 Power Manager (PM)
30.1 Overview
30.2 Features
30.3 Clocks
30.4 Interrupts
30.5 Debug Operation
30.6 Register Access Protection
30.7 Block Diagram
30.8 Functional Description
30.9 Peripheral Dependencies
30.10 Register Summary
31 Reset Controller (RSTC)
31.1 Overview
31.2 Features
31.3 Block Diagram
31.4 Signals Description
31.5 Functional Description
31.6 Peripheral Dependencies
31.7 Register Summary
32 External Interrupt Controller (EIC)
32.1 Overview
32.2 Features
32.3 Block Diagram
32.4 Signal Description
32.5 Product Dependencies
32.6 Functional Description
32.7 Sleep Mode Operation
32.8 Secure Access Right
32.9 Synchronization
32.10 Peripheral Dependencies
32.11 Register Summary
33 Non-Volatile Memory Controller (NVMCTRL)
33.1 Flash Controller Write (FCW) Module
33.2 Flash Controller Read (FCR) Module
33.3 Peripheral Dependencies
33.4 Peripheral Dependencies
33.5 Register Summary
33.6 Register Summary
34 Event System (EVSYS)
34.1 Overview
34.2 Features
34.3 Block Diagram
34.4 Power Management
34.5 Clocks
34.6 Functional Description
34.7 Peripheral Dependencies
34.8 Register Summary
35 I/O Pin Controller (PORT)
35.1 Overview
35.2 Features
35.3 Block Diagram
35.4 Signal Description
35.5 I/O Lines
35.6 Clocks
35.7 Power Management
35.8 Debug Operation
35.9 Register Access Protection
35.10 Analog Connections
35.11 PIC32CM SG Specific Secure Access Protection
35.12 Functional Description
35.13 Peripheral Dependencies
35.14 Register Summary
36 Serial Communication Interface (SERCOM)
36.1 Overview
36.2 Features
36.3 Block Diagram
36.4 Functional Description
36.5 Synchronous and Asynchronous Receiver and Transmitter (SERCOM USART)
36.6 SERCOM Serial Peripheral Interface (SPI)
36.7 SERCOM I2C
36.8 Peripheral Dependencies
36.9 Register Summary - USART
36.10 Register Summary - SPI
36.11 Register Summary - I2CM
36.12 Register Summary - I2CS
37 Controller Area Network (CAN)
37.1 Overview
37.2 Features
37.3 Block Diagram
37.4 Signal Description
37.5 Functional Description
37.6 Message RAM
37.7 Peripheral Dependencies
37.8 Register Summary
37 Rx Buffer and FIFO Element Register Summary
37 Tx Buffer Element Register Summary
37 Tx Event FIFO Element Register Summary
37 Standard Message ID Filter Element Register Summary
37 Extended Message ID Filter Element Register Summary
38 Universal Serial Bus (USB)
38.1 Overview
38.2 Features
38.3 USB Block Diagram
38.4 Signal Description
38.5 Product Dependancies
38.6 Functional Description
38.7 Peripheral Dependencies
38.8 Common Device Host Register Summary
38.9 Register Summary - DEVICE
38.10 Register Summary - HOST
38 USB Descriptor Register Summary
39 Configurable Custom Logic (CCL)
39.1 Overview
39.2 Features
39.3 Block Diagram
39.4 Signal Description
39.5 I/O Lines
39.6 Power Management
39.7 Clocks
39.8 Events
39.9 Debug Operation
39.10 Register Access Protection
39.11 Functional Description
39.12 Events
39.13 Sleep Mode Operation
39.14 Peripheral Dependencies
39.15 Register Summary
40 Analog to Digital Converter (ADC)
40.1 Overview
40.2 Features
40.3 Block Diagram
40.4 Signal Description
40.5 Functional Description
40.6 Peripheral Dependencies
40.7 Register Summary
41 Analog Comparator (AC)
41.1 Overview
41.2 Features
41.3 Block Diagram
41.4 Analog Connections
41.5 Functional Description
41.6 Peripheral Dependencies
41.7 Register Summary
41.8 Host Interrupt Flag
Host Interrupt Flag
42 Timer/Counter for Control Applications (TCC)
42.1 Overview
42.2 Features
42.3 Block Diagram
42.4 Signal Description
42.5 Functional Description
42.6 Peripheral Dependencies
42.7 Register Summary
43 TrustRAM (TRAM)
43.1 Overview
43.2 Features
43.3 Block Diagram
43.4 Functional Description
43.5 Peripheral Dependencies
43.6 Register Summary
44 Peripheral Touch Controller (PTC)
44.1 Overview
44.2 Features
44.3 Block Diagram
44.4 Signal Description
44.5 Peripheral Dependencies
44.6 Functional Description
44.7 Peripheral Dependencies
45 Hardware Security Module Lite (HSM-Lite)
45.1 Overview
45.2 Features
45.3 Operation
45.4 Cryptographic Accelerators
45.5 True Random Number Generator
45.6 PUF Interface
45.7 Peripheral Dependencies
45.8 Register Summary
46 Anti-Tamper Module (AT)
46.1 Overview
46.2 Operation
46.3 Tamper Response
46.4 Block Diagram
46.5 Register Summary
47 Physically Uncloneable Function (PUF)
47.1 Overview
47.2 Operation
47.3 Key Generation
47.4 Enrollment
47.5 Zeroization
47.6 Register Summary
48 Electrical Characteristics
48.1 Absolute Maximum Electrical Characteristics
48.2 Operating Frequencies and Thermal Specifications
48.3 Power Supply
48.4 Active Power
48.5 Idle Power
48.6 Standby Power
48.7 Hibernate Power
48.8 Backup Power
48.9 OFF Power
48.10 Wake-Up Timing
48.11 Peripheral Active Power
48.12 I/O Pin Electrical Characteristics
48.13 Internal Voltage Reference Electrical Specifications (IVREF)
48.14 Maximum Clock Frequencies
48.15 XOSC Electrical Characteristics
48.16 XOSC32K Electrical Characteristics
48.17 OSCULP32K Electrical Characteristics
48.18 DFLL-FDPLL Electrical Characteristics
48.19 Analog-to-Digital Converter (ADC) Electrical Specifications
48.20 Analog Comparator (AC) Electrical Characteristics
48.21 Peripheral Touch Controller (PTC) Electrical Characteristics
48.22 Serial Peripheral Interface (SPI) Timings Electrical Characteristics
48.23 Universal Asynchronous Receiver/Transmitter (UART) Electrical Characteristics
48.24 I2C Electrical Characteristics
48.25 Controller Area Network (CAN) Electrical Characteristics
48.26 Timer/Counter Controller (TCC) Electrical Characteristics
48.27 Universal Serial Bus (USB) Electrical Characteristics
48.28 Flash Controller Electrical Characteristics
48.29 Frequency Meter (FREQM) Electrical Characteristics
48.30 JTAG Electrical Characteristics
48.31 SWD 2-Wire Electrical Characteristics
48.32 Configurable Custom Logic (CCL) Electrical Specifications
48.33 User LDO Electrical Specifications
48.34 Multi-Channel Ram Controller (MCRAMC) Electrical Specifications
49 Electrical Characteristics 125°C
49.1 Absolute Maximum Ratings
49.2 Operating Frequencies and Thermal Specifications
49.3 MCU Active Power
49.4 Idle Power
49.5 Standby Power
49.6 Hibernate Power
49.7 Backup Power
49.8 Power Off
49.9 Maximum Clock Frequencies
49.10 Analog Comparator (AC) Electrical Specifications
49.11 Serial Peripheral Interface (SPI) Timings and Electrical Characteristics
49.12 Timer/Counter Controller (TCC) Electrical Characteristics
49.13 JTAG Electrical Specifications
50 Packaging Information
50.1 Package Marking Information
50.2 Package Drawings
50.3 Soldering Profile
51 Schematic Checklist
51.1 Introduction
52 Common Conventions
52.1 Numerical Notation
52.2 Memory Size and Type
52.3 Frequency and Time
52.4 Registers and Bits
53 Acronyms and Abbreviations
54 Revision History
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature

DS60001921A

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