37.2 Tx Event FIFO Element 1

Table 37-92. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: E1
Offset: 0x004
Reset: 0x00000000
Property: RW

Bit 3130292827262524 
 MM[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 ET[1:0]FDFBRSDLC[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 TXTS[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 TXTS[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:24 – MM[7:0] Message Marker

Copied from Tx Buffer into Tx Event FIFO element for identification of Tx message status

Bits 23:22 – ET[1:0] Event Type

This field defines the event type

ValueNameDescription
0x0 or 0x3RES

Reserved

0x1TXE

Tx event

0x2TXC

Transmission in spite of cancellation (always set for transmission in DAR mode)

Bit 21 – FDF FD Format

ValueDescription
0

Standard frame format.

1

CAN FD frame format (new DLC-coding and CRC).

Bit 20 – BRS Bit Rate Search

ValueDescription
0

Frame received without bit rate switching.

1

Frame received with bit rate switching.

Bits 19:16 – DLC[3:0] Data Length Code

ValueDescription
0-8

CAN + CAN FD: received frame has 0-8 data bytes

9-15

CAN: received frame has 8 data bytes.

9-15

CAN FD: received frame has 12/16/20/24/32/48/64 data bytes

Bits 15:0 – TXTS[15:0] Tx Timestamp

Timestamp Counter value captured on start of frame transmission. Resolution depending on configuration of the Timestamp Counter Prescaler TSCC.TCP.