12.3 SRAM Memory Configuration

Retention

In Standby and Hibernate modes, all SRAM is retained.

RAM Error Correction

For safety applications, the PIC32CM SG00 family of devices embed SRAM error correction codes (ECC) to detect and correct single bit errors, or to enable dual-error detection for the system memory. The ECC feature can be enabled or disabled after reset through the BOOTCFG1.BOOT_FLAG.RAM_INIT_ENB fuse.

DS60001921A

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