36.4.1 Principle of Operation

The basic structure of the SERCOM serial engine is shown in the following figure.

  • The transmitter consists of a single write buffer and a Shift register.
  • The receiver consists of a one-level (I2C), two-level (USART, SPI) receive buffer and a Shift register.

The Baud Rate Generator (BRG) is capable of running on the GCLK_SERCOMn_CORE clock or an external clock.

Address matching logic is included for the SPI and I2C operation.

Figure 36-2. SERCOM Serial Engine