36.12.5 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR) On read, a bit value of zero indicates the associated interrupt is disabled while a bit value of one indicates the associated interrupt is enabled.
Table 36-70. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: RW

Bit 76543210 
 ERROR  RXFFTXFEDRDYAMATCHPREC 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 7 – ERROR Combined Error Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.

ValueDescription
0Error interrupt is disabled.
1Error interrupt is enabled.

Bit 4 – RXFF Rx FIFO Full Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the RX FIFO Full bit, which enables the RX FIFO Full interrupt.

ValueDescription
0The RX FIFO Full interrupt is disabled.
1The RX FIFO Full interrupt is enabled.

Bit 3 – TXFE Tx FIFO Empty Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the TX FIFO Empty bit, which enables the TX FIFO Empty interrupt.

ValueDescription
0The TX FIFO Empty interrupt is disabled.
1The TX FIFO Empty interrupt is enabled.

Bit 2 – DRDY Data Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Data Ready bit, which enables the Data Ready interrupt.

ValueDescription
0The Data Ready interrupt is disabled.
1The Data Ready interrupt is enabled.

Bit 1 – AMATCH Address Match Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match interrupt.

ValueDescription
0The Address Match interrupt is disabled.
1The Address Match interrupt is enabled.

Bit 0 – PREC Stop Received Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Stop Received Interrupt Enable bit, which enables the Stop Received interrupt.

ValueDescription
0The Stop Received interrupt is disabled.
1The Stop Received interrupt is enabled.