37.1 Standard Message ID Filter Element
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | S0 |
| Offset: | 0x000 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SFT[1:0] | SFEC[2:0] | SFID1[10:8] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SFID1[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SFID2[10:8] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SFID2[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:30 – SFT[1:0] Standard Filter Type
This field defines the standard filter type
| Value | Name | Description |
|---|---|---|
| 0 | RANGE | Range filter from SFID1 to SFID2 |
| 1 | DUAL | Dual ID filter for SFID1 or SFID2 |
| 2 | CLASSIC | Classic filter |
Bits 29:27 – SFEC[2:0] Standard Filter Element Configuration
All enabled filter elements are used for acceptance filtering of standard frames. Acceptance filtering stops at the first matching enabled filter element or when the end of the filter list is reached. If SFEC = “100”, “101”, or “110” a match sets interrupt flag IR.HPM and, if enabled, an interrupt is generated. In this case register HPMS is updated with the status of the priority match.
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Disable filter element |
| 1 | STF0M | Store in Rx FIFO 0 if filter match |
| 2 | STF1M | Store in Rx FIFO 1 if filter match |
| 3 | REJECT | Reject ID if filter match |
| 4 | PRIORITY | Set priority if filter match |
| 5 | PRIF0M | Set priority and store in FIFO 0 if filter match |
| 6 | PRIF1M | Set priority and store in FIFO 1 if filter match |
| 7 | STRXBUF | Store into Rx Buffer |
Bits 26:16 – SFID1[10:0] Standard Filter ID 1
First ID of standard ID filter element.When filtering for Rx Buffers or for debug messages this field defines the ID of a standard mesage to be stored. The received identifiers must match exactly, no masking mechanism is used.
Bits 10:0 – SFID2[10:0] Standard Filter ID 2
This bit field has a different meaning depending on the configuration of SFEC.
1. SFEC = “001” ... “110”: Second ID of standard ID filter element.
2. SFEC = “111”: Filter for Rx Buffers or for debug messages.
SFID2[10:9] decides whether the received message is stored into an Rx Buffer or treated as message A, B, or C of the debug message sequence.
00 = Store message into an Rx Buffer
01 = Debug Message A
10 = Debug Message B
11 = Debug Message C
SFID2[8:6] is reserved for future usage.
SFID2[5:0] defines the offset to the Rx Buffer Start Address RXBC.RBSA for storage of a matching message