36.5.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read.

• The Software Reset bit in the CTRLA register (CTRLA.SWRST)
• The Enable bit in the CTRLA register (CTRLA.ENABLE)
• The Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
• The Transmitter Enable bit in the Control B register (CTRLB.TXEN)

Required write synchronization is denoted by the Write-Synchronized property in the register description. If a write-synchronized register is written while a synchronization is ongoing, a Bus Error exception will be generated.