Jump to main content
ATECC608B-TFLXTLS CryptoAuthentication™ Data Sheet
Search
Product Pages
ATECC608B
Home
7
I
2
C Interface
7.1
I/O Conditions
Introduction
Features
Use Cases
1
Pin Configuration and Pinouts
2
EEPROM Memory and Data Zone Access Policies
3
Static RAM (SRAM) Memory
4
General Command Information
5
Device Commands
6
Application Information
7
I
2
C Interface
7.1
I/O Conditions
7.1.1
Device is Asleep
7.1.2
Device is Awake
7.2
I
2
C Transmission to
ATECC608B-TFLXTLS
7.3
Sleep Sequence
7.4
Idle Sequence
7.5
I
2
C Transmission from the
ATECC608B-TFLXTLS
8
Single-Wire Interface
9
Electrical Characteristics
10
Compatibility
11
Package Drawings
12
Revision History
Microchip Information
7.1 I/O Conditions
The device responds to the following I/O conditions:
