5.2.1 TSCAL DATA from SRAM0

During development phases, when the OTP is not yet programmed or not used in Emulation mode, TSCAL data can only be accessed from SRAM0 at a specific address. This address is available in the CPU register R6 when the ROM code hands over to the bootstrap. The R6 register is filled when loading and executing a bootstrap, not when launching the SAM-BA Monitor. See “Boot Interface” in the “Boot Strategies” section of the SAMA7D6 Series data sheet (see Reference Documents).

Warning: To avoid data corruption by the application, we strongly advise against accessing TSCAL data from SRAM0 at any time other than during early development. Loading a second level bootloader program may (depending on size) already corrupt TSCAL data.
Warning: The TSCAL data physical address in SRAM0 may change with a ROM code update. Always use CPU register R6 (at ROM code exit) to retrieve this address independently of the ROM code revision.

In the SRAM, the data is formatted like the original OTP engineering packet, with:

  • a header (Checksum and Lock data cleared),
  • a tag to identify the packet content,
  • the payload.

Packet structure example:

  • Header: 1x 32-bit word
  • Payload [0]: "TSCA"
  • Payload [1-4]: data
    • Temperature Sensor Calibration Data