21.3.8 SMTxCLK
SMT Clock Selection Register
| Name: | SMTxCLK |
| Offset: | 0x049B |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CSEL[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 2:0 – CSEL[2:0] SMT Clock Selection bits
| CSEL[2:0] | Clock Source |
|---|---|
111 | CLKREF output |
110 | SOSC |
101 | MFINTOSC (31.25kHz) |
100 | MFINTOSC (500kHz) |
011 | LFINTOSC |
010 | HFINTOSC |
001 | FOSC |
000 | FOSC/4 |