10.12 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and PCON0 registers are updated to indicate the cause of the Reset. The following tables show the Reset conditions of these registers.
| STOVF | STKUNF | RWDT | RMCLR | RI | POR | BOR | TO | PD | MEMV | Condition |
|---|---|---|---|---|---|---|---|---|---|---|
0 | 0 | 1 | 1 | 1 | 0 | x | 1 | 1 | 1 | Power-on Reset |
0 | 0 | 1 | 1 | 1 | 0 | x | 0 | x | u | Illegal, TO is set on POR |
0 | 0 | 1 | 1 | 1 | 0 | x | x | 0 | u | Illegal, PD is set on POR |
0 | 0 | u | 1 | 1 | u | 0 | 1 | 1 | u | Brown-out Reset |
u | u | 0 | u | u | u | u | 0 | u | u | WWDT Reset |
u | u | u | u | u | u | u | 0 | 0 | u | WWDT Wake-up from Sleep |
u | u | u | u | u | u | u | 1 | 0 | u | Interrupt Wake-up from Sleep |
u | u | u | 0 | u | u | u | u | u | 1 | MCLR Reset during normal operation |
u | u | u | 0 | u | u | u | 1 | 0 | u | MCLR Reset during Sleep |
u | u | u | u | 0 | u | u | u | u | u | RESET instruction executed |
1 | u | u | u | u | u | u | u | u | u | Stack Overflow Reset (STVREN = 1) |
u | 1 | u | u | u | u | u | u | u | u | Stack Underflow Reset (STVREN = 1) |
u | u | u | u | u | u | u | u | u | 0 | Memory Violation Reset |
| Condition | Program Counter | STATUS Register | PCON0 Register | PCON1 Register |
|---|---|---|---|---|
| Power-on Reset | 0 | ---1
1000 | 0011
110x | ---- --1- |
| Brown-out Reset | 0 | ---1
1000 | 0011
11u0 | ---- --u- |
| MCLR Reset during normal operation | 0 | -uuu
uuuu | uuuu
0uuu | ---- --1- |
| MCLR Reset during Sleep | 0 | ---1
0uuu | uuuu
0uuu | ---- --u- |
| WWDT Time-out Reset | 0 | ---0
uuuu | uuu0
uuuu | ---- --u- |
| WWDT Wake-up from Sleep | PC + 1 | ---0
0uuu | uuuu
uuuu | ---- --u- |
| WWDT Window Violation Reset | 0 | ---u
uuuu | uu0u
uuuu | ---- --u- |
| Interrupt Wake-up from Sleep | PC + 1(1) | ---1
0uuu | uuuu
uuuu | ---- --u- |
RESET instruction executed | 0 | ---u
uuuu | uuuu
u0uu | ---- --u- |
Stack Overflow Reset (STVREN = 1) | 0 | ---u
uuuu | 1uuu
uuuu | ---- --u- |
Stack Underflow Reset (STVREN =
1) | 0 | ---u
uuuu | u1uu
uuuu | ----
--u- |
Memory Violation
Reset (MEMV = 0) | 0 | -uuu
uuuu | uuuu
uuuu | ---- --0- |
Legend:
u = unchanged, x = unknown, — = unimplemented bit, reads
as ‘0’.
Note:
- When the wake-up is due to an interrupt and the Global Enable (GIE) bit is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.