1.2.1 TCE - 16-Bit Timer/Counter Type E

The flexible 16-bit PWM provides accurate program execution timing, frequency and waveform generation, and command execution. The Timer/Counter consists of a base counter and compare channels. You may use the base counter to count clock cycles or events or to allow events to dictate clock cycle counting. The counting direction and period setting control are used for accurate timing. You may use the compare channels with the base counter for compare match control, frequency generation, and PWM.

A timer/counter can be clocked and timed from the peripheral clock, with optional prescaling, or from the Event System (EVSYS). The EVSYS can also be used to control direction or synchronize operations.

The counter register (TCEn.CNT), period registers with buffer (TCEn.PER and TCEn.PERBUF), and compare registers with buffers (TCEn.CMPn and TCEn.CMPBUFn) are 16-bit registers. All buffer registers use a buffer valid (BV) flag that indicates when the buffer contains a new value.

During ordinary operation, the counter value is compared continuously to zero and the Period (PER) value to determine whether the counter has reached TOP or BOTTOM.

The counter includes a high-resolution option that can increase the duty cycle resolution by up to eight times the input clock. The counter value is also compared to the TCEn.CMPn registers. These comparisons can generate interrupt requests. The waveform generator modes use these comparisons to set the waveform period or pulse width.

When the scaled write is enabled, the values written to the CMPn/CMPnBUF are between 0 and 1.99, giving a duty-cycle range between 0% and 100% of the PWM period, as shown below.

BLACK line – Normal full-scale CMP write.

RED line – CMP values when AMP is 90%.