12.2.1 diag_simple_wdt_fsm_state_t Enum
The following is an UML Test State diagram forSimple Watchdog Timer test: .
- DIAG_WDT_SIMPLE_FSM_FAULT
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0 - is assigned to WDT Test State in case of faults
- DIAG_WDT_SIMPLE_FSM_TEST
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1 - is assigned to WDT Test State to perform WDT Simple Timer Test
- DIAG_WDT_SIMPLE_FSM_OK
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2 - is assigned to WDT Test State on error-free execution of DIAG_WDT_SIMPLE_FSM_TEST