11.1.2 SRAM_MARCH_CLK_FRQ
#define SRAM_MARCH_CLK_FRQ (CLKCTRL_PDIV_2X_gc | CLKCTRL_PEN_bm)Sets the main clock frequency used when running the SRAM March diagnostic test (the clock frequency will be set back to default upon completing the test). A higher main clock frequency than the default value will reduce the worst case execution time (WCET) of the SRAM March diagnostic test. Depending on the device, the frequency can be set by defining the macro value as any CLKCTRL_FRQSEL_t group configuration (e.g. CLKCTRL_FRQSEL_24M_gc) or CLKCTRL_PDIV_t group configuration (e.g CLKCTRL_PDIV_2X_gc). The former option, if available for the device in use (such as the AVR DA family of devices), can set the frequency directly regardless of the supply voltage to the device.
The latter option divides the main clock source frequency (which can depend on FUSE settings), if the PEN bit is also set, with the specified value. Thus, when configuring with the latter option, ensure that CLKCTRL_PEN_bm is bitwise ORed with the CLKCTRL_PDIV_t group configuration
(e.g. SRAM_MARCH_CLK_FRQ (CLKCTRL_PDIV_2X_gc | CLKCTRL_PEN_bm)". If the PEN bit is not set, the test will run with no main clock prescaler and thus at full main clock source speed. The system integrator must ensure that this frequency doesnot exceed the maximum specified frequency with the used device supply voltage and specified temperature range.