27.12.3 MDSRC

Modulation Source Control Register

Name:	MDSRC
Offset:	0xF53


Bit	7	6	5	4	3	2	1	0
				SRCS[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – SRCS[4:0] Modulator Source Selection bits

Table 27-1. MDSRC Selection MUX Connections
SRCS[4:0]	Connection
`11000-11111`	Reserved
`10111`	MSSP2 - SDO
`10110`	MSSP1 - SDO
`10101`	EUSART5 TX (TX/CK output)
`10100`	EUSART5 RX (DT output)
`10011`	EUSART4 TX (TX/CK output)
`10010`	EUSART4 RX (DT output)
`10001`	EUSART3 TX (TX/CK output)
`10000`	EUSART3 RX (DT output)
`01111`	EUSART2 TX (TX/CK output)
`01110`	EUSART2 RX (DT output)
`01101`	EUSART1 TX (TX/CK output)
`01100`	EUSART1 RX (DT output)
`01011`	CMP3 OUT
`01010`	CMP2 OUT
`01001`	CMP1 OUT
`01000`	PWM7 OUT
`00111`	PWM6 OUT
`00110`	CCP5 OUT
`00101`	CCP4 OUT
`00100`	CCP3 OUT
`00011`	CCP2 OUT
`00010`	CCP1 OUT
`00001`	MDBIT
`00000`	Pin selected by MDSRCPPS

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