2.3 Details on Individual Family Members
Devices in the PIC18(L)F65/66K40 family are available in 64-pin packages. The block diagram for this device is shown in the Figure 2-1.
The devices have the following differences:
- Program Flash Memory
- Data Memory SRAM
- Data Memory EEPROM
- Analog-to-Digital (A/D) channels
- I/O ports
- Enhanced USART
- Input Voltage Range/Power Consumption
All other features for devices in this family are identical. These are summarized in the following Device Features table.
The pinouts for all devices are listed in the pin summary tables.
Features | PIC18(L)F65K40 | PIC18(L)F66K40 |
---|---|---|
Program Memory (Bytes) | 32768 | 65536 |
Program Memory (Instructions) | 16384 | 32768 |
Data Memory (Bytes) | 2048 | 3562 |
Data EEPROM Memory (Bytes) | 1024 | 1024 |
I/O Ports | A,B,C,D,E,F,G(1),H | A,B,C,D,E,F,G(1),H |
Capture/Compare/PWM Modules (CCP) | 5 | |
10-Bit Pulse-Width Modulator (PWM) | 2 | |
10-Bit Analog-to-Digital Module (ADC2) with Computation Accelerator | 4
internal 47 external | |
Packages | 64-pin TQFP 64-pin QFN | |
Interrupt Sources | 56 | |
Timers (16-/8-bit) | 5/4 | |
Serial Communications | 2
MSSP, 5 EUSART | |
Enhanced Complementary Waveform Generator (ECWG) | 1 | |
Signal Measurement Timer (SMT) | 2 | |
Comparators | 3 | |
Zero-Cross Detect (ZCD) | 1 | |
Data Signal Modulator (DSM) | 1 | |
Peripheral Pin Select (PPS) | Yes | |
Peripheral Module Disable (PMD) | Yes | |
16-bit CRC with NVMSCAN | Yes | |
Programmable High/Low-Voltage Detect (HLVD) | Yes | |
Programmable Brown-out Reset (BOR) | Yes | |
Resets (and Delays) | POR, BOR,
Stack Overflow, Stack Underflow, MCLR, WWDT, (PWRT, OST) | |
Instruction Set | 75
Instructions; 83 with Extended Instruction Set enabled | |
Operating Frequency | DC – 64 MHz | |
Note 1: RG5 is an input-only pin. |