3.3.5.11.1 Global Configuration

  1. Update the SFRBU DDR Power Control register (SFRBU_DDRPWR) to take the DDR I/Os out of Retention state.
    • Wait for the command to complete by polling bit SFRBU_DDRPWR.RETENTION until it sets to 1.
  2. Update the RSTC Generic Reset register (RSTC_GRSTR) to reset the DDR PHY and DDR controllers.
  3. Perform a dummy read to allow 128 cycles for synchronization.
  4. Update RSTC_GRSTR to release the DDR3PHY reset.
  5. Perform a dummy read to allow 128 cycles for synchronization.