3.1.3.4.1 LPDDR2 Power Failure Management

The DDR controller (UDDRC and DDR3PHY) is used to manage the LPDDR memory when an uncontrolled power off occurs.

The DDR power rail must be monitored externally and generate an interrupt when a power fail condition is triggered.

The interrupt handler must apply a reset to DDR3PHY by resetting bit RSTC_GRSTR.DDR_PHY_RST. Reset will tie the CKE signal to '0' on the DDR interface.