3.2.2 Embedded Characteristics

  • 128 Mbytes Address Space per Chip Select
  • 8- or 16-bit Data Bus
  • Word, Halfword, Byte Transfers
  • Byte Write or Byte Select Lines
  • Programmable Setup, Pulse and Hold Time for Read Signals per Chip Select
  • Programmable Setup, Pulse and Hold Time for Write Signals per Chip Select
  • Programmable Data Float Time per Chip Select
  • External Data Bus Scrambling/Unscrambling Function
  • External Wait Request
  • Automatic Switch to Slow Clock Mode
  • Hardware Configurable Number of Chip Selects from 1 to 4
  • Programmable Timing on a per Chip Select Basis
  • NAND Flash Controller Supporting NAND Flash with Multiplexed Data/Address Buses
  • Supports SLC and MLC NAND Flash Technology
  • Supports NAND Flash Devices with 8 or 16-bit Data Paths
  • Multibit Error Correcting Code (ECC) supporting NAND Flash devices with 8-bit only Data Path
  • ECC Algorithm Based on Binary Shortened Bose, Chaudhuri and Hocquenghem (BCH) Codes
  • Programmable Error Correcting Capability: 2, 4, 8, 12, 24 and 32 bits of Errors per Block
  • 9 Kbytes NFC SRAM (NFC_RAM)
  • Programmable Block Size: 512 bytes or 1024 bytes
  • Programmable Number of Blocks per Page: 1, 2, 4 or 8 Blocks of Data per Page
  • Programmable Spare Area Size up to 512 bytes
  • Supports Spare Area ECC Protection
  • Supports 8 Kbytes Page Size Using 1024 bytes/block and 4 Kbytes Page Size Using 512 bytes/block
  • Multibit Error Detection Is Interrupt Driven
  • Provides Hardware Acceleration for Determining Roots of Polynomials Defined over a Finite Field
  • Programmable Finite Field GF(2^13) or GF(2^14)
  • Finds Roots of Error-locator Polynomial
  • Programmable Number of Roots
  • Register Write Protection

  • Compatible with Open NAND Flash Interface (ONFI) 1.0 (only modes 0,1, 2 and 3 are supported)

Note:
  1. The ONFI 1.0 specification is available at www.onfi.org.