2.2.1.3 AHB Subsystem
The following tables summarize the AHB matrix hosts and clients.
| Host Port | Port Name |
|---|---|
| CPU from AXI | M0 |
| XDMAC[1:0] from AXI | M1 |
|
GMAC[1:0] from AXI SDMMC[2:0] from AXI XDMAC2 from AXI | M2 |
| MCAN0 | M3 |
| MCAN1 | M4 |
| MCAN2 | M5 |
| MCAN3 | M6 |
| MCAN4 | M7 |
| MCAN5 | M8 |
| ICM | M9 |
| UDPHS0_DMA | M10 |
| UDPHS1_DMA | M11 |
| OHCI_DMA | M12 |
| EHCI_DMA | M13 |
| TZAESB | M14 |
| Client Port | Port Name |
|---|---|
| QSPI0 | S0 |
| QSPI1 | S1 |
| TZAESB | S2 |
| UDDRC_P1 | S3 |
| APB6 | S4 |
| SRAM_P0 | S5 |
| SRAM_P1 | S6 |
| SMC(1) | S7 |
| NFC_RAM | S8 |
| USB_RAM | S9 |
Note:
- The Static Memory Controller (SMC) contains several configurable memory areas. These are EBI_CS0, EBI_CS1, EBI_CS2, EBI_CS3 and NFC_CMD, with respective HSEL from HSEL0 to HSEL4.
To improve performance, a transaction QoS can be both generated and handled by the matrix. See Quality of Service (QoS) Overview.