Jump to main content
Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
Search
Product Pages
SAMA7G54
Home
3
Memories
3.3
Universal DDR Memory Controller (UDDRC)
3.3.5
Functional Description
3.3.5.14
Power Saving Features
3.3.5.14.1
SDRAM Power Saving Features
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
3.1
Overview
3.2
Static Memory Controller (SMC)
3.3
Universal DDR Memory Controller (UDDRC)
3.3.1
Description
3.3.2
Embedded Characteristics
3.3.3
Block Diagram
3.3.4
I/O Lines Description
3.3.5
Functional Description
3.3.5.1
AXI Port Interface (XPI)
3.3.5.2
Port Arbiter (PA)
3.3.5.3
Address Mapper
3.3.5.4
Address Collision Handling
3.3.5.5
Quality of Service (QoS)
3.3.5.6
Bypass Operation
3.3.5.7
Burst Mode Operation
3.3.5.8
Refresh Controls
3.3.5.9
ZQ Calibration
3.3.5.10
ODT Control
3.3.5.11
High-Level SDRAM Initialization Procedure
3.3.5.12
Mode Register Reads and Writes
3.3.5.13
2T Memory Command Timing
3.3.5.14
Power Saving Features
3.3.5.14.1
SDRAM Power Saving Features
3.3.5.14.1.1
Precharge Power-down
3.3.5.14.1.2
Deep Power-Down
3.3.5.14.1.3
Assertion of dfi_dram_clk_disable
3.3.5.14.1.4
DLL-Off Mode (DDR3)
3.3.5.14.2
Power Saving in PHY through DFI Low-Power Interface
3.3.5.14.3
Software Sequence for Removal of Clocks
3.3.5.14.4
Power Removal Flow
3.3.5.14.5
Registers Related to Power-Saving Features
3.3
Register Summary
3.4
DDR/LPDDR Physical Interface (DDR3PHY)
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
3.3.5.14.1 SDRAM Power Saving Features
