The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Name:
SPDIFRX_IMR
Offset:
0x18
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
CP_ERR
PRE_ERR
NRZ_ERR
BLOCKST
SECE
C2SC
C1SC
Access
W
W
W
W
R
R
R
Reset
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RXFULL
OVERRUN
PAR_ERR
SFE
BLOCKEND
LOSS
LOCKED
RXRDY
Access
R
R
R
W
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit 14 – CP_ERR 16 Consecutive Preamble Errors Interrupt
Enable
Bit 13 – PRE_ERR Preamble Error (Code
Violation) Interrupt Mask
Bit 12 – NRZ_ERR NRZ Biphase Mark
Error in Payload Data (Code Violation) Interrupt Mask
Bit 11 – BLOCKST Start of Block
Interrupt Mask
Bit 10 – SECE Security Report Interrupt Mask
Bit 9 – C2SC Bit 0 to 31 Channel 2 Status Change Interrupt Mask
Bit 8 – C1SC Bit 0 to 31 Channel 1 Status Change Interrupt Mask
Bit 7 – RXFULL Receiver FIFO Full Interrupt Mask
Bit 6 – OVERRUN FIFO Overrun, Interrupt Mask
Bit 5 – PAR_ERR Parity Bit Error Interrupt Mask
Bit 4 – SFE Sampling Frequency Change Event Interrupt
Mask
Bit 3 – BLOCKEND End of Block Interrupt Mask
Bit 2 – LOSS Loss of Signal Activity While Locked Interrupt
Mask
Bit 1 – LOCKED Receiver Synchronized Interrupt Mask
Bit 0 – RXRDY Receive Data Ready Interrupt Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
