7.4.7.2 SPDIF Receiver Mode Register
This register can only be written if the WPEN bit is cleared in the SPDIF Receiver Write Protection Mode Register.
| Name: | SPDIFRX_MR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| AUTORST | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SBMODE | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PACK | DATAWIDTH[1:0] | PBMODE | ENDIAN | VBMODE | RXEN | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 24 – AUTORST Consecutive Preamble Error Threshold Automatic Restart
| Value | Name | Description |
|---|---|---|
| 0 | NOACTION | No action whatever the number of consecutive preamble errors found during the period where SPDIFRX_RSR.ULOCK=0. |
| 1 | UNLOCK_ON_PRE_ERR | If 16 consecutive preamble errors are detected, the clock recovery circuitry is restarted. |
Bit 8 – SBMODE Start of Block Bit Mode
| Value | Name | Description |
|---|---|---|
| 0 | ALWAYS_LOAD | Whatever the preamble code, the sample is loaded in FIFO. |
| 1 | DISCARD | The sample is loaded in FIFO only if a Start of Block is detected. |
Bit 7 – PACK Packed Data Mode in Receive Holding Register
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | Each read of SPDIFRX_RHR contains 1 sample and additional information (validity bit, parity bit, user data bit, channel status bit, byte 0 bit 1 of channel status and type of frame carrying the sample). |
| 1 | ENABLED | The 32-bit SPDIFRX_RHR contains only payload data. Depending on the value of SPDIFRX_MR.DATAWIDTH, the alignment of data differs. This mode optimizes the amount of system memory required to manage the samples. |
Bits 5:4 – DATAWIDTH[1:0] Sample Data Width
| Value | Name | Description |
|---|---|---|
| 0 | 24BIT | The complete data field is stored in FIFO. |
| 1 | 20BIT | Only the 20 MSB are stored in the FIFO. |
| 2 | 16BIT | Only the 16 MSB are stored in the FIFO. |
| 3 | Reserved | Reserved |
Bit 3 – PBMODE Parity Bit Mode
| Value | Name | Description |
|---|---|---|
| 0 | PARCHECK | Parity check enabled on data payload |
| 1 | NOPARCHECK | No parity check on data payload |
Bit 2 – ENDIAN Data Word Endian Mode
| Value | Name | Description |
|---|---|---|
| 0 | LITTLE | Little-endian mode for 24-bit samples |
| 1 | BIG | Big-endian mode for 24-bit samples |
Bit 1 – VBMODE Validity Bit Mode
| Value | Name | Description |
|---|---|---|
| 0 | ALWAYS_LOAD | Whatever the validity bit value is, the sample is loaded in FIFO. |
| 1 | DISCARD_IF_VB1 | The sample is loaded in FIFO only if the validity bit equals 0. |
Bit 0 – RXEN SPDIF Receive Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | The SPDIF receiver is disabled. |
| 1 | ENABLE | The SPDIF receiver is enabled. |