7.4.7.3 SPDIF Receiver Interrupt Enable Register

This register can only be written if the WPITEN bit is cleared in the SPDIF Receiver Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name: SPDIFRX_IER
Offset: 0x10
Reset: –
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
  CP_ERRPRE_ERRNRZ_ERRBLOCKSTSECEC2SCC1SC 
Access WWWWWWW 
Reset ––––––– 
Bit 76543210 
 RXFULLOVERRUNPAR_ERRSFEBLOCKENDLOSSLOCKEDRXRDY 
Access WWWWWWWW 
Reset –––––––– 

Bit 14 – CP_ERR 16 Consecutive Preamble Errors Interrupt Enable

Bit 13 – PRE_ERR Preamble Error (Code Violation) Enable

Bit 12 – NRZ_ERR NRZ Biphase Mark Error in Payload Data (Code Violation) Enable

Bit 11 – BLOCKST Start of Block Interrupt Enable

Bit 10 – SECE Security Report Interrupt Enable

Bit 9 – C2SC Bit 0 to 31 Channel 2 Status Change Interrupt Enable

Bit 8 – C1SC Bit 0 to 31 Channel 1 Status Change Interrupt Enable

Bit 7 – RXFULL Receiver FIFO Full Interrupt Enable

Bit 6 – OVERRUN FIFO Overrun, Interrupt Enable

Bit 5 – PAR_ERR Parity Bit Error Interrupt Enable

Bit 4 – SFE Sampling Frequency Change Event Interrupt Enable

Bit 3 – BLOCKEND End of Block Interrupt Enable

Bit 2 – LOSS Loss of Signal Activity While Locked Interrupt Enable

Bit 1 – LOCKED Receiver Synchronized Interrupt Enable

Bit 0 – RXRDY Receive Data Ready Interrupt Enable