1.12 Peripheral Identifiers

Table 1-6. Peripheral Identifiers
Instance ID	Instance  Name	Security	TZ  Security  Management	GIC SPI  Interrupt	External  Interrupt	PMC Clock Control	Main System Bus  Clock	Max. Generic  Clock Freq. (MHz)⁽¹⁾	SYSPLLCK	DDRPLLCK	IMGPLLCK	BAUDPLLCK	AUDIOPLLCK	ETHPLLCK	Instance  Description
0	DWDT	AS	–	SW	–	–	MCK0	–	–	–	–	–	–	–	Dual Watchdog Timer, Secure World
1	DWDT	NS	–	NSW	–	–	MCK0	–	–	–	–	–	–	–	Dual Watchdog Timer, Non-secure World
2	DWDT	AS	–	NSW_ALARM	–	–	MCK0	–	–	–	–	–	–	–	Dual Watchdog Timer, Non-secure World Alarm
4	SCKC	AS	–	–	–	–	MCK0	–	–	–	–	–	–	–	Slow Clock Controller
5	SHDWC	AS	–	–	–	–	MCK0	–	–	–	–	–	–	–	Shutdown Controller
6	RSTC	AS	–	X	–	–	MCK0	–	–	–	–	–	–	–	Reset Controller
7	RTC	AS	–	X	–	–	MCK0	–	–	–	–	–	–	–	Real-Time Clock
8	RTT	AS	–	X	–	–	MCK0	–	–	–	–	–	–	–	Real-Time Timer
9	CHIPID	PS	TZPM	–	–	–	MCK0	–	–	–	–	–	–	–	Chip Identifier
10	PMC	AS	–	X	–	–	MCK0	–	–	–	–	–	–	–	Power Management Controller
11	PIOA	PS	PIOA	X	–	X	MCK0	–	–	–	–	–	–	–	For PIO 0 to 31
12	PIOB	PS	PIOB	X	–	–	MCK0	–	–	–	–	–	–	–	For PIO 32 to 63
13	PIOC	PS	PIOC	X	–	–	MCK0	–	–	–	–	–	–	–	For PIO 64 to 95
14	PIOD	PS	PIOD	X	–	–	MCK0	–	–	–	–	–	–	–	For PIO 96 to 127
15	PIOE	PS	PIOE	X	–	–	MCK0	–	–	–	–	–	–	–	For PIO 128 to 135
17	SECUMOD	AS	–	X	–	–	MCK0	–	–	–	–	–	–	–	Security Module
18	SECURAM	AS	–	X	–	–	MCK0	–	–	–	–	–	–	–	Secure Backup SRAM
19	SFR	PS	TZPM	–	–	X	MCK1	–	–	–	–	–	–	–	Special Function Register
20	SFRBU	AS	–	–	–	–	MCK0	–	–	–	–	–	–	–	Special Function Register in Backup zone
21	HSMC	PS	MATRIX + TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	Static Memory Controller – NAND Flash Controller
22	XDMAC0	PS	XDMAC0	X	–	X	MCK1	–	–	–	–	–	–	–	DMA 0, mem to periph, 32 channels
23	XDMAC1	PS	XDMAC1	X	–	X	MCK1	–	–	–	–	–	–	–	DMA 1, mem to periph, 32 channels
24	XDMAC2	PS	XDMAC2	X	–	X	MCK1	–	–	–	–	–	–	–	DMA 2, mem to mem, 8 channels
25	ACC	PS	TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	Analog Comparator Controller
26	ADC	PS	TZPM	X	–	–	GCLK⁽²⁾	100	X	–	–	X	X	–	Analog-to-Digital Converter
27	AES	PS	TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	Advanced Encryption Standard
28	TZAESBASC	AS	TZPM	–	–	X	MCK1	–	–	–	–	–	–	–	TrustZone Advanced Encryption Standard Bridge – Address Space Controlller
29	ARM	PS	MMU	–	–	–	MCK1	50	X	X	–	–	X	–	Cortex-A7 Core 0
30	ASRC	PS	TZPM	X	–	X	MCK1	200	X	–	–	–	X	–	Asynchronous Sample Rate Converter
32	CPKCC	PS	TZPM	X	–	X	MCK0	–	–	–	–	–	–	–	Classic Public Key Cryptography Controller
33	CSI	PS	TZPM	X	–	X	MCK3	27	X	–	X	–	–	–	Camera Serial Interface 2 between ISC and MIPI PHY
34	CSI2DC	PS	TZPM	X	–	X	MCK3	–	–	–	–	–	–	–	CSI to Demultiplexer Controller
35	DDR3PHY	PS	TZC + TZPM	–	–	–	MCK2	–	–	–	–	–	–	–	DDR/LPDDR Physical Interface
36	UDDRC	PS	TZC + TZPM	–	–	–	MCK2	–	–	–	–	–	–	–	Universal DDR Memory Controller
37	EIC	PS	TZPM	–	–	X	MCK1	–	–	–	–	–	–	–	External Interrupt Controller
38	FLEXCOM0	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	–	X	–	–	FLEXCOM 0
39	FLEXCOM1	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	–	X	–	–	FLEXCOM 1
40	FLEXCOM2	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	–	X	–	–	FLEXCOM 2
41	FLEXCOM3	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	–	X	–	–	FLEXCOM 3
42	FLEXCOM4	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	–	X	–	–	FLEXCOM 4
43	FLEXCOM5	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	–	X	–	–	FLEXCOM 5
44	FLEXCOM6	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	–	X	–	–	FLEXCOM 6
45	FLEXCOM7	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	–	X	–	–	FLEXCOM 7
46	FLEXCOM8	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	–	X	–	–	FLEXCOM 8
47	FLEXCOM9	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	–	X	–	–	FLEXCOM 9
48	FLEXCOM10	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	–	X	–	–	FLEXCOM 10
49	FLEXCOM11	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–		X	–	–	FLEXCOM 11
51	GMAC0	PS	TZPM	X	–	X	MCK1	125	–	–	–	–	–	X	Gigabit Ethernet MAC
52	GMAC1	PS	TZPM	X	–	X	MCK1	50	–	–	–	–	–	X	Ethernet MAC
53	GMAC0	PS	same as GMAC0	TSU	–	–	MCK1	200	–	–	–	–	X	X	Gigabit Ethernet MAC – Timestamp Unit Generic Clock – No Interrupt
54	GMAC1	PS	same as GMAC1	TSU	–	–	MCK1	200	–	–	–	–	X	X	Ethernet MAC – Timestamp Unit Generic Clock – No Interrupt
55	ICM	AS	TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	Integrity Check Monitor
56	ISC	PS	TZPM	X	–	X	MCK3	–	–	–	–	–	–	–	Camera Interface
57	I2SMCC0	PS	TZPM	X	–	X	MCK1	100	X	–	–	–	X	–	Inter-IC Sound Controller 0
58	I2SMCC1	PS	TZPM	X	–	X	MCK1	100	X	–	–	–	X	–	Inter-IC Sound Controller 1
60	MATRIX	AS	–	X	–	–	MCK1	–	–	–	–	–	–	–	AHB Matrix
61	MCAN0	PS	TZPM	INT0	–	X	MCK1	80	X	–	–	X	–	–	Host CAN 0
62	MCAN1	PS	TZPM	INT0	–	X	MCK1	80	X	–	–	X	–	–	Host CAN 1
63	MCAN2	PS	TZPM	INT0	–	X	MCK1	80	X	–	–	X	–	–	Host CAN 2
64	MCAN3	PS	TZPM	INT0	–	X	MCK1	80	X	–	–	X	–	–	Host CAN 3
65	MCAN4	PS	TZPM	INT0	–	X	MCK1	80	X	–	–	X	–	–	Host CAN 4
66	MCAN5	PS	TZPM	INT0	–	X	MCK1	80	X	–	–	X	–	–	Host CAN 5
67	OTPC	PS	TZPM	X	–	–	MCK0	–	–	–	–	–	–	–	One Time Programmable Memory Controller
68	PDMC0	PS	TZPM	X	–	X	MCK1	50	X	–	–	–	X	–	Pulse Density Modulation Interface Controller 0
69	PDMC1	PS	TZPM	X	–	X	MCK1	50	X	–	–	–	X	–	Pulse Density Modulation Interface Controller 1
70	PIT64B0	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	X	X	X	X	64-bit Periodic Interval Timer 0
71	PIT64B1	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	X	X	X	X	64-bit Periodic Interval Timer 1
72	PIT64B2	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	X	X	X	X	64-bit Periodic Interval Timer 2
73	PIT64B3	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	X	X	X	X	64-bit Periodic Interval Timer 3
74	PIT64B4	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	X	X	X	X	64-bit Periodic Interval Timer 4
75	PIT64B5	PS	TZPM	X	–	X	MCK1	f_MCK1/3	X	–	X	X	X	X	64-bit Periodic Interval Timer 5
77	PWM	PS	TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	Pulse Width Modulation
78	QSPI0	PS	MATRIX + TZPM	X	–	X	MCK1	200	X	–	–	X	–	–	Quad IO Serial Peripheral Interface 0
79	QSPI1	PS	MATRIX + TZPM	X	–	X	MCK1	200	X	–	–	X	–	–	Quad IO Serial Peripheral Interface 1
80	SDMMC0	PS	TZPM	X	–	X	MCK1	208	X	–	X	X	–	X	Ultra High Speed SD Host Controller 0 (e.MMC 5.1)
81	SDMMC1	PS	TZPM	X	–	X	MCK1	208	X	–	X	X	–	X	Ultra High Speed SD Host Controller 1 (e.MMC 4.51)
82	SDMMC2	PS	TZPM	X	–	X	MCK1	208	X	–	X	X	–	X	Ultra High Speed SD Host Controller 2 (e.MMC 4.51)
83	SHA	PS	TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	Secure Hash Algorithm
84	SPDIFRX	PS	TZPM	X	–	X	MCK1	150	X	–	–	–	X	–	Sony Philips Digital Interface RX
85	SPDIFTX	PS	TZPM	X	–	X	MCK1	25	X	–	–	–	X	–	Sony Philips Digital Interface TX
86	SSC0	PS	TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	Synchronous Serial Interface 0
87	SSC1	PS	TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	Synchronous Serial Interface 1
88	TC0	PS	TZPM	CHANNEL0	–	X	MCK1	f_MCK1/3	X	–	X	X	X	X	32-bit Timer Counter 0 Channel 0
89	TC0	PS	same as channel0	CHANNEL1	–	X	MCK1	–	–	–	–	–	–	–	32-bit Timer Counter 0 Channel 1
90	TC0	PS	same as channel0	CHANNEL2	–	X	MCK1	–	–	–	–	–	–	–	32-bit Timer Counter 0 Channel 2
91	TC1	PS	TZPM	CHANNEL0	–	X	MCK1	f_MCK1/3	X	–	X	X	X	X	32-bit Timer Counter 1 Channel 0
92	TC1	PS	same as channel0	CHANNEL1	–	X	MCK1	–	–	–	–	–	–	–	32-bit Timer Counter 1 Channel 1
93	TC1	PS	same as channel0	CHANNEL2	–	X	MCK1	–	–	–	–	–	–	–	32-bit Timer Counter 1 Channel 2
94	TCPCA	PS	TZPM	X	–	X	MCK1	⁽³⁾	–	–	–	–	–	–	USB Type-C Port Controller A
95	TCPCB	PS	TZPM	X	–	X	MCK1	⁽³⁾	–	–	–	–	–	–	USB Type-C Port Controller B
96	TDES	PS	TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	Triple Data Encryption Standard
97	TRNG	PS	TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	True Random Number Generator
98	TZAESB	PS	TZPM	NS	–	X	MCK1	–	–	–	–	–	–	–	TrustZone Advanced Encryption Standard Bridge Non–Secure (Clocks & Interrupt)
99	TZAESB	AS	–	NS_INT	–	–	MCK1	–	–	–	–	–	–	–	TrustZone Advanced Encryption Standard Bridge Non–Secure (Interrupt only)
100	TZAESB	PS	TZPM	S	–	–	MCK1	–	–	–	–	–	–	–	TrustZone Advanced Encryption Standard Bridge Secure (Interrupt only)
101	TZAESB	AS	–	S_INT	–	–	MCK1	–	–	–	–	–	–	–	TrustZone Advanced Encryption Standard Bridge Secure (Interrupt only)
102	TZC	AS	AS	X	–	–	MCK1	–	–	–	–	–	–	–	TrustZone Address Space Controller (TZC-400)
104	UDPHSA	PS	MATRIX + TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	USB Device High Speed A
105	UDPHSB	PS	MATRIX + TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	USB Device High Speed B
106	UHPHS	PS	MATRIX + TZPM	X	–	X	MCK1	–	–	–	–	–	–	–	USB Host Controller High Speed
110	ARM	PS	MMU	nPMUIRQ	–	–	MCK1	–	–	–	–	–	–	–	Performance Monitoring Unit
111	ARM	PS	MMU	nAXIERRIRQ	–	–	MCK1	–	–	–	–	–	–	–	AXI Transaction Error
112	XDMAC0	PS	XDMAC0	SINT	–	–	MCK1	–	–	–	–	–	–	–	DMA0, mem to periph, 32 channels, Secure Interrupt
113	XDMAC1	PS	XDAMC1	SINT	–	–	MCK1	–	–	–	–	–	–	–	DMA1, mem to periph, 32 channels, Secure Interrupt
114	XDMAC2	PS	XDMAC2	SINT	–	–	MCK1	–	–	–	–	–	–	–	DMA2, mem to mem, 8 channels, Secure Interrupt
115	AES	PS	same as AES	SINT	–	–	MCK1	–	–	–	–	–	–	–	Advanced Encryption Standard, Secure Interrupt
116	GMAC0	PS	same as GMAC0	Q1	–	–	MCK1	–	–	–	–	–	–	–	GMAC0 Queue 1 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 1
117	GMAC0	PS	same as GMAC0	Q2	–	–	MCK1	–	–	–	–	–	–	–	GMAC0 Queue 2 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 2
118	GMAC0	PS	same as GMAC0	Q3	–	–	MCK1	–	–	–	–	–	–	–	GMAC0 Queue 3 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 3
119	GMAC0	PS	same as GMAC0	Q4	–	–	MCK1	–	–	–	–	–	–	–	GMAC0 Queue 4 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 4
120	GMAC0	PS	same as GMAC0	Q5	–	–	MCK1	–	–	–	–	–	–	–	GMAC0 Queue 5 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 5
121	GMAC1	PS	same as GMAC1	Q1	–	–	MCK1	–	–	–	–	–	–	–	GMAC1 Queue 1 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 1
122	ICM	AS	same as ICM	–	–	–	MCK1	–	–	–	–	–	–	–	Integrity Check Monitor, Secure Interrupt
123	MCAN0	PS	same as MCAN0	INT1	–	–	MCK1	–	–	–	–	–	–	–	MCAN0 Interrupt1
124	MCAN1	PS	same as MCAN1	INT1	–	–	MCK1	–	–	–	–	–	–	–	MCAN1 Interrupt1
125	MCAN2	PS	same as MCAN2	INT1	–	–	MCK1	–	–	–	–	–	–	–	MCAN2 Interrupt1
126	MCAN3	PS	same as MCAN3	INT1	–	–	MCK1	–	–	–	–	–	–	–	MCAN3 Interrupt1
127	MCAN4	PS	same as MCAN4	INT1	–	–	MCK1	–	–	–	–	–	–	–	MCAN4 Interrupt1
128	MCAN5	PS	same as MCAN5	INT1	–	–	MCK1	–	–	–	–	–	–	–	MCAN5 Interrupt1
129	PIOA	PS	same as PIOA	SINT	–	–	MCK0	–	–	–	–	–	–	–	For PIO 0 to 31, Secure Interrupt
130	PIOB	PS	same as PIOB	SINT	–	–	MCK0	–	–	–	–	–	–	–	For PIO 32 to 63, Secure Interrupt
131	PIOC	PS	same as PIOC	SINT	–	–	MCK0	–	–	–	–	–	–	–	For PIO 64 to 95, Secure Interrupt
132	PIOD	PS	same as PIOD	SINT	–	–	MCK0	–	–	–	–	–	–	–	For PIO 96 to 127, Secure Interrupt
133	PIOE	PS	same as PIOE	SINT	–	–	MCK0	–	–	–	–	–	–	–	For PIO 128 to 136, Secure Interrupt
140	PIT64B5	PS	same as PIT64B5	SINT	–	–	MCK1	–	–	–	–	–	–	–	64-bit Periodic Interval Timer 5, Secure Interrupt
141	SDMMC0	PS	same as SDMMC0	TIMER	–	–	MCK1	–	–	–	–	–	–	–	Ultra High Speed SD Host Controller 0 (e.MMC 5.1) Timer interrupt
142	SDMMC1	PS	same as SDMMC1	TIMER	–	–	MCK1	–	–	–	–	–	–	–	Ultra High Speed SD Host Controller 1 (e.MMC 4.51) Timer interrupt
143	SDMMC2	PS	same as SDMMC2	TIMER	–	–	MCK1	–	–	–	–	–	–	–	Ultra High Speed SD Host controller 2 (e.MMC 4.51) Timer interrupt
144	SHA	PS	same as SHA	SINT	–	–	MCK1	–	–	–	–	–	–	–	Secure Hash Algorithm, Secure Interrupt
151	TDES	PS	same as TDES	SINT	–	–	MCK1	–	–	–	–	–	–	–	Triple Data Encryption Standard, Secure Interrupt
152	TRNG	PS	same as TRNG	SINT	–	–	MCK1	–	–	–	–	–	–	–	True Random Number Generator, Secure Interrupt
153	EIC	PS	same as EIC	X	EXT_IRQ0	–	MCK1	–	–	–	–	–	–	–	External Interrupt ID0
154	EIC	PS	same as EIC	X	EXT_IRQ1	–	MCK1	–	–	–	–	–	–	–	External Interrupt ID1
Note: A Generic Clock (GCLK) is associated with the peripheral identifiers that have a value in the Max. Generic Clock Freq. column. In addition to the PLL sources shown in the table, the following GCLK sources are also available for all peripherals (except 94 and 95, that only support MD_SLCK and TD_SLCK): MD_SLCK, TD_SLCK, MAINCK and MCK0. WARNING: GCLK must be started before accessing registers. Select GCLK input as MD_SLCK or TD_SLCK.