7.2.7.9 I2SMCC Interrupt Enable Register B

This register can only be written if WPITEN is cleared in the Inter-IC Sound Write Protection Mode Register.

The following configuration values are valid for the listed bits of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name: I2SMCC_IERB
Offset: 0x20
Reset: –
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   RXFFFULRXFFRDY  TXFFEMPTXFFRDY 
Access WWWW 
Reset –––– 
Bit 76543210 
        WERR 
Access W 
Reset – 

Bit 13 – RXFFFUL RX FIFO Full Interrupt Enable

Bit 12 – RXFFRDY RX FIFO Ready Interrupt Enable

Bit 9 – TXFFEMP TX FIFO Empty Interrupt Enable

Bit 8 – TXFFRDY TX FIFO Ready Interrupt Enable

Bit 0 – WERR Write Error Interrupt Enable