Jump to main content
4.7.6.22 RTC TimeStamp Source Register This register is cleared
after read and the read access also performs a clear on RTC_TSTRx and RTC_TSDRx.The following configuration values are valid for all listed bit
names of this register:
0: No alarm generated since the
last clear.
1: An alarm has been generated by the
corresponding monitor since the last clear.
Name: RTC_TSSRx Offset: 0xB8 + x*0x0C [x=0..1] Reset: 0x00000000 Property: Read-only
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 DET3 DET2 DET1 DET0 Access R R R R Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 Access Reset
Bit 7 6 5 4 3 2 1 0 JTAG TST DWDTSW Access R R R Reset 0 0 0
Bits 18, 19, 20, 21 – DETx PIOBU Intrusion Detector (cleared on read)
Bit 3 – JTAG JTAG Pins Monitor (cleared on
read)
Bit 2 – TST Test Pin Monitor (cleared on
read)
Bit 0 – DWDTSW Dual WatchDog Timer
Event (cleared on read)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
