9.3.10.10 USART Interrupt Mask Register (Default Mode)

For LIN-specific configurations, see USART Interrupt Mask Register (LIN_MODE).

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is not enabled.

1: The corresponding interrupt is enabled.

Name: FLEX_US_IMR (DEFAULT_MODE)
Offset: 0x210
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
        MANE 
Access R 
Reset 0 
Bit 2322212019181716 
  CMP  CTSIC    
Access RR 
Reset 00 
Bit 15141312111098 
   NACK  ITERTXEMPTYTIMEOUT 
Access RRRR 
Reset 0000 
Bit 76543210 
 PAREFRAMEOVRE  RXBRKTXRDYRXRDY 
Access RRRRRR 
Reset 000000 

Bit 24 – MANE Manchester Error Interrupt Mask

Bit 22 – CMP Comparison Interrupt Mask

Bit 19 – CTSIC Clear to Send Input Change Interrupt Mask

Bit 13 – NACK Non Acknowledge Interrupt Mask

Bit 10 – ITER Max Number of Repetitions Reached Interrupt Mask

Bit 9 – TXEMPTY TXEMPTY Interrupt Mask

Bit 8 – TIMEOUT Timeout Interrupt Mask

Bit 7 – PARE Parity Error Interrupt Mask

Bit 6 – FRAME Framing Error Interrupt Mask

Bit 5 – OVRE Overrun Error Interrupt Mask

Bit 2 – RXBRK Receiver Break Interrupt Mask

Bit 1 – TXRDY TXRDY Interrupt Mask

Bit 0 – RXRDY RXRDY Interrupt Mask