2 Example Overview

CCL can be used as a simple logic block for pin logic. A code example with three I/O pin inputs can be found in the Quick Start Guide for CCL in ASF. In the following application example a more advanced use case is presented. This example shows how CCL can be used with TCs, together with Event System and DMAC, to generate an IR encoded signal. The project developed using ASF is available for download as an attachment, along with this Application Note. Before the example is presented, it is necessary to have a brief introduction to IR encoding.

IR Encoding

There are many different standards for IR encoding. Most of them involve a fixed carrier frequency which will be on for a certain period and then off for a certain period. The enabling and disabling of the carrier frequency is determined by the dutycycle of a waveformed modulation signal. The dutycycle of the modulation signal will then determine if the transmitting value is a start pulse, a logical one or a logical zero. E.g. if the carrier frequency is signaled 3/4 of the period, this indicates a logical one, while 1/4 indicates a logical zero. This is illustrated in the following figure.
Figure 2-1. IR Encoded Signal
In the following example, no specific encoding will be applied but a more general approach where period and dutycycle can be adjusted is presented.

Implementation

To generate a modulated IR signal, CCL is configured with two TC inputs while the last input is masked. The default TC is used to generate the carrier frequency of the IR signal while the alternative TC is applied as the modulation signal. To ensure the modulation signal is synchronized with the carrier frequency, the alternative TC increments on overflow events generated by the default TC. In the example, the truth table is written to 0x01. Referring to the Table 1-6, this corresponds to a high output when alternative TC waveform is low and default TC waveform is high. By adjusting the compare value for the alternative TC, the dutycycle will change, resulting in longer or shorter intervals of transmitting the carrier frequency.

To update compare value and period, the DMAC will be setup with two channels transferring data from two arrays in memory to the dedicated TC registers. Using DMAC to update the compare value register and the peroid register allows the device to operate from Standby sleep mode.

An illustration of the application flow is shown in Figure 2-2.

In the following sections, only code for CCL configuration is attached. The configuration of TC, DMAC and EVSYS will be described but the implementation is only available in the example project enclosed to this application note.

Figure 2-2. Schematic of Implementation