27.5.6 Host Status
| Name: | MSTATUS |
| Offset: | 0x05 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RIF | WIF | CLKHOLD | RXACK | ARBLOST | BUSERR | BUSSTATE[1:0] | |||
| Access | R/W | R/W | R/W | R | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – RIF Read Interrupt Flag
This flag is set to ‘1’ when the host byte read operation is
completed.
The RIF flag can be used for a host read interrupt. More information can be found in the Read Interrupt Enable (RIEN) bit from the Host Control A (TWIn.MCTRLA) register.
This flag is automatically cleared when accessing several other TWI registers. The RIF flag can be cleared by choosing one of the following methods:
- Writing a ‘
1’ to it. - Writing to the Host Address (TWIn.MADDR) register.
- Writing/Reading the Host Data (TWIn.MDATA) register.
- Writing to the Command (MCMD) bit field from the Host Control B (TWIn.MCTRLB) register.
Bit 6 – WIF Write Interrupt Flag
This flag is set to ‘1’ when a host transmit address or byte
write operation is completed, regardless of the occurrence of a bus error or
arbitration lost condition.
The WIF flag can be used for a host write interrupt. More information can be found from the Write Interrupt Enable (WIEN) bit in the Host Control A (TWIn.MCTRLA) register.
This flag can be cleared by choosing one of the methods described for the RIF flag.
Bit 5 – CLKHOLD Clock Hold
When this bit is read as ‘1’, it indicates that the host is
currently holding the SCL low, stretching the TWI clock period.
This bit can be cleared by choosing one of the methods described for the RIF flag.
Bit 4 – RXACK Received Acknowledge
When this flag is read as ‘0’, it indicates that the most recent
Acknowledge bit from the client was ACK, and the client is ready for more
data.
When this flag is read as ‘1’, it indicates that the most recent
Acknowledge bit from the client was NACK, and the client is not able to or does
not need to receive more data.
Bit 3 – ARBLOST Arbitration Lost
When this bit is read as ‘1’, it indicates that the host has
lost arbitration. This can happen in one of the following cases:
- While transmitting a high data bit.
- While transmitting a NACK bit.
- While issuing a Start condition (S).
- While issuing a repeated Start (Sr).
This flag can be cleared by choosing one of the methods described for the RIF flag.
Bit 2 – BUSERR Bus Error
The BUSERR flag indicates that an illegal bus operation has occurred. An illegal bus operation is detected if a protocol violating the Start (S), repeated Start (Sr), or Stop (P) conditions is detected on the TWI bus lines. A Start condition directly followed by a Stop condition is one example of a protocol violation.
The BUSERR flag can be cleared by choosing one of the following methods:
- Writing a ‘
1’ to it. - Writing to the Host Address (TWIn.MADDR) register.
The TWI bus error detector is part of the TWI host circuitry. For the bus errors
to be detected, the TWI host must be enabled (ENABLE bit in TWIn.MCTRLA is
‘1’), and the main clock frequency must be at least four
times the SCL frequency.
Bits 1:0 – BUSSTATE[1:0] Bus State
This bit field indicates the current TWI bus state. Writing 0x1
to this bit field will force the bus state to IDLE. All other values will be
ignored.
| Value | Name | Description |
|---|---|---|
| 0x0 | UNKNOWN | Unknown bus state |
| 0x1 | IDLE | Idle bus state |
| 0x2 | OWNER | This TWI controls the bus |
| 0x3 | BUSY | Busy bus state |