27.5.10 Client Control A
| Name: | SCTRLA |
| Offset: | 0x09 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIEN | APIEN | PIEN | PMEN | SMEN | ENABLE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – DIEN Data Interrupt Enable
Writing this bit to ‘1’ enables an interrupt on the Data
Interrupt Flag (DIF) from the Client Status (TWIn.SSTATUS) register.
A TWI client data interrupt will be generated only if this bit, the DIF flag, and
the Global Interrupt Enable (I) bit in Status (CPU.SREG) register are all
‘1’.
Bit 6 – APIEN Address or Stop Interrupt Enable
Writing this bit to ‘1’ enables an interrupt on the Address or
Stop Interrupt Flag (APIF) from the Client Status (TWIn.SSTATUS) register.
A TWI client address or stop interrupt will be generated only if this bit, the
APIF flag, and the Global Interrupt Enable (I) bit in the Status (CPU.SREG)
register are all ‘1’.
- The client stop interrupt shares the interrupt flag and vector with the client address interrupt.
- The Stop Interrupt Enable
(PIEN) bit in the Client Control A (TWIn.SCTRLA) register must be
written to ‘
1’ for the APIF to be set on a Stop condition. - When the interrupt occurs, the Address or Stop (AP) bit in the Client Status (TWIn.SSTATUS) register will determine whether an address match or a Stop condition caused the interrupt.
Bit 5 – PIEN Stop Interrupt Enable
Writing this bit to ‘1’ allows the Address or Stop Interrupt
Flag (APIF) in the Client Status (TWIn.SSTATUS) register to be set when a Stop
condition occurs. To use this feature, the main clock frequency must be at least
four times the SCL frequency.
Bit 2 – PMEN Address Recognition Mode
If this bit is written to ‘1’, the client address match logic
responds to all received addresses.
If this bit is written to ‘0’, the address match logic uses the
Client Address (TWIn.SADDR) register to determine which address to recognize as
the client’s address.
Bit 1 – SMEN Smart Mode Enable
Writing this bit to ‘1’ enables the client Smart mode. When the
Smart mode is enabled, issuing a command by writing to the Command (SCMD) bit
field in the Client Control B (TWIn.SCTRLB) register or accessing the Client
Data (TWIn.SDATA) register resets the interrupt, and the operation continues. If
the Smart mode is disabled, the client always waits for a new client command
before continuing.
Bit 0 – ENABLE Enable TWI Client
Writing this bit to ‘1’ enables the TWI client.