37.15 TWI

Figure 37-7. TWI - Timing Requirements
Table 37-21. TWI - Timing Specifications
SymbolDescriptionMin.Typ.✝Max.UnitCondition
VDDSupply voltage range1.8—5.5VfSCL ≤ 400 kHz
2.2 *—5.5 *fSCL ≤ 1 MHz
fSCL *SCL clock frequency——1000kHzMax. frequency requires system clock at 10 MHz
VHYS *Hysteresis of Schmitt Trigger inputs0.05×VDD0.4×VDDV
VOLOutput low voltage——0.4VIload = 5 mA, VDD > 2V
——0.2×VDDIload = 3 mA, VDD ≤ 2V
IOL *Low-level output current5——mAVOL = 0.4V
10——VOL = 0.4V

VDD ≥ 2.7V

CB *Capacitive load for each bus line——400pFfSCL ≤ 100 kHz
——400fSCL ≤ 400 kHz
——550

fSCL ≤ 1 MHz

VDD > 2.75V

tR *Rise time for both SDA and SCL——1000nsfSCL ≤ 100 kHz
20—300fSCL ≤ 400 kHz
——120fSCL ≤ 1 MHz
tOF *Output fall time from VIHmin to VILmax——250ns

fSCL ≤ 100 kHz

10 pF < CB < 400 pF

20×(VDD/5.5V)—250

fSCL ≤ 400 kHz

10 pF < CB < 400 pF

20×(VDD/5.5V)—120

fSCL ≤ 1 MHz

10 pF < CB < 400 pF

tSP *Spikes suppressed by the input filter0—50ns
IL *Input current for each I/O pin——1µA0.1×VDD < VI < 0.9×VDD
CI *Capacitance for each I/O pin——10pF
RP *Value of pull-up resistor(VDD-VOL(max)) /IOL—1000 ns/(0.8473×CB)ΩfSCL ≤ 100 kHz
(VDD-VOL(max)) /IOL—300 ns/(0.8473×CB)fSCL ≤ 400 kHz
(VDD-VOL(max)) /IOL—120 ns/(0.8473×CB)fSCL ≤ 1 MHz
tHD_STA *Hold time (repeated) Start condition4.0——µsfSCL ≤ 100 kHz
0.6——fSCL ≤ 400 kHz
0.26——fSCL ≤ 1 MHz
TLOW *Low period of SCL Clock4.7——µsfSCL ≤ 100 kHz
0.6——fSCL ≤ 400 kHz
0.35——fSCL ≤ 1 MHz
THIGH *High period of SCL Clock4.0——µsfSCL ≤ 100 kHz
0.6——fSCL ≤ 400 kHz
0.26——fSCL ≤ 1 MHz
tSU_STA *Setup time for a repeated Start condition4.7——µsfSCL ≤ 100 kHz
0.6——fSCL ≤ 400 kHz
0.26——fSCL ≤ 1 MHz
tHD_DAT *Data hold time across all corners—0—nsSDAHOLD[1:0] = 0x0
300—900SDAHOLD[1:0] = 0x3
tSU_DAT *Data setup time250——nsfSCL ≤ 100 kHz
100——fSCL ≤ 400 kHz
50——fSCL ≤ 1 MHz
tSU_STO *Setup time for Stop condition4——µsfSCL ≤ 100 kHz
0.6——fSCL ≤ 400 kHz
0.26——fSCL ≤ 1 MHz
tBUF *Bus free time between a Stop and Start condition4.7——µsfSCL ≤ 100 kHz
1.3——fSCL ≤ 400 kHz
tCS *Client Clock Stretching delay——250ns

✝ Data found in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

* These parameters are characterized but not tested in production.