3.5 Configuration Straps

Configuration straps allow features of the device to be automatically configured to user defined values based on signal levels at reset. They are identified by an underlined signal name in the pin assignment lists. Configuration straps do not have internal resistors to prevent the signal from floating when unconnected.

Important: The configuration straps are shared on pins with output signals. Pins identified as configuration straps must always be pulled high to VDDP or low to VSS through an external resistor.
Important: External pull-up or pull-down resistors must be sized appropriately (10 kΩ, typical) to ensure that the configuration straps reach the required voltage level prior to latching at reset. If a pull-up resistor is used, it must be connected to VDDP.

Configuration straps are latched on Power-On Reset (POR) and pin reset (RESET_N). At the completion of the reset, that is when all power supplies are above the thresholds and the RESET_N pin is no longer asserted the signals are sampled and stored in the STRAP_CTRL0.

Note: When a soft reset occurs via the Soft Reset bit of the Basic Control Register, the configuration of the device is reloaded from the STRAP_CTRL0 register, not from the state of the external pins. To ensure proper operation, the values in this register should never be changed.

MODE[0] and MODE[1] Configuration Straps

Only the LAN8670 and LAN8672 have configuration strap pins labeled MODE[0] and MODE[1]. These pins shall be configured as follows.

LAN8670 - Configuring Device Mode

The MODE[1:0] configuration straps determine whether the interface from the LAN8670 to the MAC is MII, RMII, or SC-MII, as shown in Table 3-12 below. The value can be read in the STRAP_CTRL0 register, if needed.

Table 3-12. MODE[1:0] Configuration Straps
MODE[1:0]Definition
00bReserved
01bPHY is placed in MII mode with 25 MHz crystal
10bPHY is placed in RMII mode with 50 MHz REFCLKIN
11b

PHY is placed in Single Clock MII (SC-MII) mode with 25 MHz crystal. (LAN8670 only)

The TXCLK and TXER pins are used for other features. The RXCLK pin becomes a single MII clock output.

LAN8672

In the LAN8672, the MODE0 shall be pulled up, and the MODE1 pin shall be pulled down to ensure proper device operation

PHYAD[] Configuration Straps - Selecting a PHY Address

In some applications, especially in switches, multiple PHYs share the same SMI, that is MDIO and MDC pins. In these systems, the controller operating the pins must be able to manage each PHY separately. This is done by assigning each device a unique address. Each PHY checks each management data frame for a matching address and each PHY will only respond to frames with its correct address.

The PHYAD[] configuration straps enable a unique address to be assigned to each PHY. The hardware design of the PHYAD[] configuration straps shall ensure that the pins are pulled high to VDDP or low to ground through external resistors during a power on or hardware reset. Each PHY on the same MDIO interface must have a unique configuration of straps to provide a unique SMI address. This address is latched into an internal register at the end of a hardware reset. Any combination of bits is valid as an address.

Note: The LAN8670/2 have five PHYAD pins for a total of 32 possible addresses. The LAN8671 has four PHYAD pins for a total of 16 possible addresses.