3.4 Pin Descriptions
This section contains descriptions of the various LAN8670/1/2 pins. The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of “active low” and “active high” signals. The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.
Pin buffer type definitions are detailed in the Buffer Types section.
| Name | Symbol | Buffer Type | Description |
|---|---|---|---|
| Transmit Data 0 | TXD0 |
VIS-VDDP PD |
Transmit data bus bit 0 (all modes). This pin is high impedance when the device is in reset. |
| Transmit Data 1 | TXD1 |
VIS-VDDP PD |
Transmit data bus bit 1 (all modes). This pin is high impedance when the device is in reset. |
| Transmit Data 2 (MII/SC-MII modes) | TXD2 |
VIS-VDDP PD |
Transmit data bus bit 2 (MII/SC-MII modes). In RMII mode, this signal is not used and is internally pulled-down to VSS. This pin is high impedance when the device is in reset. |
| Transmit Data 3 (MII/SC-MII modes) | TXD3 |
VIS-VDDP PD |
Transmit data bus bit 3 (MII/SC-MII modes). In RMII mode, this signal is not used and is internally pulled-down to VSS. This pin is high impedance when the device is in reset. |
| Transmit Error (MII mode) | TXER |
VIS-VDDP PD |
This input is asserted to indicate that an error was detected somewhere in the packet presently being transferred to the device. This pin is unused in RMII mode and should be connected to VSS if it is not used for ACMA functionality on the LAN8670. This pin is shared with the ACMA functionality on the LAN8670. This pin is high impedance when the device is in reset. |
| Transmit Enable | TXEN |
VIS-VDDP PD |
Indicates that valid transmission data is present on TXD[3:0]. In RMII mode, only TXD[1:0] provide valid data. Note: A pull-down resistor is recommended to prevent incidental transmission if
the MAC does not actively pull-down or drive this pin low at all times
during its reset and initialization.
This pin is high impedance when the device is in reset. |
| Transmit Clock (MII mode) | TXCLK | VO-VDDP |
2.5 MHz clock used to latch data from the MAC into the device. In RMII mode, this pin is unused and is driven low. It should be left unconnected if it is not used for RXPI functionality on the LAN8670. This pin is shared with the RXPI functionality on the LAN8670. This pin is high impedance when the device is in reset. |
| Receive Data 0 | RXD0 | VOH-VDDP |
Receive data bus bit 0 (all modes). This pin shares functionality as a PHYAD2 configuration strap and, therefore, must be connected to VDDP/VSS through a pull‑up/pull‑down resistor, as desired. This pin is an input when the device is in reset. The state of this pin is captured as PHYAD2 as the device exits reset. |
| Receive Data 1 | RXD1 | VOH-VDDP |
Receive data bus bit 1 (all modes). This pin shares functionality as a PHYAD3 configuration strap and, therefore, must be connected to VDDP/VSS through a pull‑up/pull‑down resistor, as desired. This pin is an input when the device is in reset. The state of this pin is captured as PHYAD3 as the device exits reset. |
| Receive Data 2 (MII/SC-MII modes) | RXD2 | VO-VDDP |
Receive data bus bit 2 (MII/SC-MII modes) This pin shares functionality as a MODE0 configuration strap and, therefore, must be connected to VDDP/VSS through a pull‑up/pull‑down resistor, as desired. When the LAN8670 is configured for RMII operation, the RXD2 signal is unused except as the MODE0 configuration strap during reset. This pin is an input when the device is in reset. The state of this pin is captured as MODE0 as the device exits reset. |
| Receive Data 3 (MII/SC-MII modes) | RXD3 | VO-VDDP |
Receive data bus bit 3 (MII/SC-MII modes). This pin shares functionality as a MODE1 configuration strap and, therefore, must be connected to VDDP/VSS through a pull‑up/pull‑down resistor, as desired. When the LAN8670 is configured for RMII operation, the RXD3 signal is unused except as the MODE1 configuration strap during reset. This pin is an input when the device is in reset. The state of this pin is captured as MODE1 as the device exits reset. |
| Receive Error | RXER | VOH-VDDP |
This output is asserted to indicate that an error was detected somewhere in the packet presently being transferred from the device. This signal is optional in RMII mode and may be left unconnected from the MAC. This pin shares functionality as a PHYAD0 configuration strap, however, and, therefore, must be connected to VDDP/VSS through a pull‑up/pull‑down resistor, as desired. This pin is an input when the device is in reset. The state of this pin is captured as PHYAD0 as the device exits reset. |
| Receive Data Valid (MII/SC-MII modes) | RXDV | VOH-VDDP |
Indicates that recovered and decoded data is available on the RXD[3:0] pins. This pin shares functionality as a PHYAD1 configuration strap and, therefore, must be connected to VDDP/VSS through a pull‑up/pull‑down resistor, as desired. When the LAN8670 is configured for RMII operation, the RXDV signal is unused except as the PHYAD1 configuration strap during reset. The pin, however, is used as CRSDV. This pin is an input when the device is in reset. The state of this pin is captured as PHYAD1 as the device exits reset. |
| Receive Clock (MII mode) | RXCLK | VO-VDDP |
In MII mode, this pin is the 2.5 MHz receive clock output. In RMII mode, this pin is unused and is driven low. It should be left unconnected if it is not used for WAKEOUT functionality on the LAN8670. This pin is shared with the WAKEOUT functionality on the LAN8670. This pin is high impedance when the device is in reset. |
| Single Media Clock (SC-MII mode) | SMCLK | VO-VDDP |
In Single Clock MII mode, this pin is the 2.5 MHz clock output to be connected to the media access controller MII TXCLK and RXCLK input pins. This pin is shared with the WAKEOUT functionality on the LAN8670. This pin is high impedance when the device is in reset. |
| Carrier Sense / Receive Data Valid (RMII mode) | CRSDV | VOH-VDDP |
This signal is asserted to indicate the receive medium is non-idle in RMII mode. This pin shares functionality as a PHYAD1 configuration strap and, therefore, must be connected to VDDP/VSS through a pull‑up/pull‑down resistor, as desired. When the LAN8670 is configured for MII or SC-MII operation, the CRSDV signal is unused except as the PHYAD1 configuration strap during reset. The pin, however, is used as RXDV. This pin is an input when the device is in reset. The state of this pin is captured as PHYAD1 as the device exits reset. |
| Collision Detect (MII/SC-MII modes) | COL | VO-VDDP |
Collision Detect. In RMII mode, this pin should be connected to VSS as it is unused and floating. This pin is high impedance when the device is in reset. |
| Carrier Sense (MII/SC-MII modes) | CRS | VO-VDDP |
Carrier Sense. This pin shares functionality as a PHYAD4 configuration strap and, therefore, must be connected to VDDP/VSS through a pull‑up/pull‑down resistor, as desired. This pin is an input when the device is in reset. The state of this pin is captured as PHYAD4 as the device exits reset. |
| Name | Symbol | Buffer Type | Description |
|---|---|---|---|
| Ethernet TX/RX Positive Terminal | TRXP | AIO | Positive terminal for transmit/receive signal. |
| Ethernet TX/RX Negative Terminal | TRXN | AIO | Negative terminal for transmit/receive signal. |
| Name | Symbol | Buffer Type | Description |
|---|---|---|---|
| SMI Data Input/Output | MDIO |
VIS-VDDP / VO-VDDP |
Serial Management Interface data input/output. Should be connected to VDDP via pull-up resistor. This pin is high impedance when the device is in reset. |
| SMI Clock | MDC | VIS-VDDP |
Serial Management Interface clock. This pin is high impedance when the device is in reset. |
| Name | Symbol | Buffer Type | Description |
|---|---|---|---|
| Inhibit | INH | VODH-VDDAU |
Inhibit. Used to switch on/off the main external voltage regulators. This pin operates in the VDDAU domain. RESET_N assertion does not affect the state of this pin. This signal is an active high P-channel open-drain source output. The pin will be driven to VDDAU to inhibit the shutdown of external voltage regulators. When the external regulators may be shutdown, this pin will become high impedance. Note: When used, this pin requires a pull-down
resistor.
When not used, this pin should be left unconnected. This pin is high impedance when the device is in reset. |
| Wake Input | WAKE_IN | VI-VDDAU |
Wake Input. Asserted to move the part out of sleep. When not used, this pin should be connected to VSS. This pin is high impedance when the device is in reset. Note: This pin operates in the VDDAU domain.
Note: When used, this pin requires a pull-up or pull-down
resistor, depending on the software configured assertion polarity. If a
pull-up is used, it must be connected to VDDAU.
|
| Wake Output | WAKE_OUT | VO-VDDP |
Wake Output. Asserted when the part wakes out of sleep. When not used, this pin should be left unconnected. This pin is high impedance when the device is in reset. Note: When used, this pin requires a pull-down
resistor.
Note: This pin operates in the VDDP domain.
|
| Name | Symbol | Buffer Type | Description |
|---|---|---|---|
| Application Controlled Medium Access | ACMA | VIS-VDDP | Application Controlled Medium Access. When this feature is
enabled, the station controller may assert this input to allow the PHY to
transmit to the medium. When unused, this pin is an input and should be connected to VSS. This pin is high impedance when the device is in reset. |
| Receive Packet Indication | RXPI | VO-VDDP | Receive Packet Indication. This pin is asserted by the Time
Synchronization block to indicate the reception of a packet. This pin may also
be asserted when the PHY receives a packet that matches a configured pattern.
The packet matching feature is typically used to trigger on reception of IEEE
Std 802.1AS gPTP packets. When unused, this pin is actively driven low and may be left unconnected. This pin is high impedance when the device is in reset. |
| Transmit Packet Indication | TXPI | VO-VDDP |
Transmit Packet Indication. This pin is asserted by the Time Synchronization block to indicate the transmission of a packet. This pin may also be asserted when the PHY transmits a packet that matches a configured pattern. The packet matching feature is typically used to trigger on transmission of IEEE Std 802.1AS gPTP packets. This pin is high impedance when the device is in reset. |
| General Purpose Application I/O | GPIO0 | VIS-VDDP / VO-VDDP | General Purpose Application I/O 0. This pin may be configured
as ACMA, TXPI, RXPI, or RXTXPI. The station management entity cannot directly drive or read this pin through CSR writes or reads. When unused, this pin is actively driven low and may be left unconnected. This pin is high impedance when the device is in reset. |
| Name | Symbol | Buffer Type | Description |
|---|---|---|---|
| External 25 MHz Crystal Input | XTI | ICLK | External 25 MHz crystal input (MII/SC-MII only). |
| External 25 MHz Crystal Output | XTO | OCLK | External 25 MHz crystal output (MII/SC-MII only). Note: When the LAN8670 is in RMII mode, this pin should be
left unconnected.
|
| External Clock Input | REFCLKIN | ICLK | 50 MHz, 1.8-3.3V single-ended clock oscillator input (RMII only). |
| Interrupt | IRQ_N | VODL-VDDP | Device interrupt request. Active low N-channel open-drain sink output. Note: This pin requires a
10 kΩ (typical) pull-up to VDDP.
This pin is high impedance when the device is in reset. |
| System Reset | RESET_N |
VIS-VDDP PU | System reset. This pin is active low. If unused, this pin may be connected directly to VDDP. |
| Bias Resistor | RBIAS | AIO | External bias resistor connection pin. This pin requires
connection of a 12.4 kΩ resistor to ground. Note: The resistor must be within
± 1% tolerance across the entire expected operating temperature
range. |
| Do Not Connect | DNC | — | The pin must be left floating externally unless otherwise directed by Microchip. |
| Name | Symbol | Buffer Type | Description |
|---|---|---|---|
| Operating Mode Configuration Straps 1-0 | MODE[1:0] | VIS-VDDP | These configuration straps are used to select the device’s
default mode of operation. See Configuration Straps for additional
information. Note: These pins must be connected to
either VDDP or VSS via a pull-up/pull-down resistor (10 kΩ, typical) to
configure the desired operating mode. |
| PHY Address Configuration Straps 4-0 | PHYAD[4:0] | VIS-VDDP | These configuration straps are used to select the device’s
default PHY SMI address. See Configuration Straps for additional
information. Note: These pins must be connected to
either VDDP or VSS via a pull-up/pull-down resistor (10 kΩ, typical) to
configure the desired SMI address. |
| Name | Symbol | Description |
|---|---|---|
| +3.3V Switchable I/O Power Supply Input | VDDP | +3.3V I/O power supply input. When in sleep mode, this supply must be disabled. |
| +3.3V Continuous VDDAU Power Supply Input | VDDAU | +3.3V continuous VDDAU power supply input. Note: This supply must be provided during sleep
mode. Note: When wake/sleep support is not used,
this pin is connected to the same supply as VDDA. |
| +3.3V Switchable Analog Power Supply Input | VDDA | +3.3V analog power supply input. When in sleep mode, this supply must be disabled. |
| Ground | VSS | Common ground. Note: This exposed pad
must be connected to the ground plane with a via array. |