5.3.1 10BASE-T1S PCS Control
| Name: | T1SPCSCTL |
| Address: | 0x08F3 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RST | LBE | DUPLEX | |||||||
| Access | R/W SC | R/W | RO | RO | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | RO | RO | RO | RO | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 – RST PCS Reset
Note: This bit is self-clearing. When setting this bit, do not set other bits in this register.
| Value | Description |
|---|---|
0 | Normal Operation |
1 | PCS reset |
Bit 14 – LBE PCS Loopback Enable
When this bit is set, data from the MAC will be passed through the PHY to the PCS and returned back to the MAC. This tests the full path from the MAC media interface through the PCS scrambler/descrambler and 4B/5B encoder/decoder.
Important: PLCA must be disabled when the PCS
loopback mode is enabled.
| Value | Description |
|---|---|
0 | Disable PCS loopback mode |
1 | Enable PCS loopback mode |
Bit 8 – DUPLEX Duplex Mode
Note: Only half-duplex operation is supported. This bit is always 1.
| Value | Description |
|---|---|
0 | Full-duplex operation |
1 | Half-duplex operation |