6.4 Power Connectivity
This section describes the typical power configuration for the LAN8670/1/2 devices with the power supply architecture and recommended decoupling.
For simple architectures, the LAN8670/1/2 requires only a single 3.3V power supply if no low power sleep state with wake-up mechanism is required. If the application requires a low power sleep state and wake-up, then an additional uninterrupted, continuous 3.3V power supply (3.3Vcont) must be connected to VDDAU to power the internal wake-up circuitry. See Figure 6-6. When a sleep power state is not required, a continuous 3.3V power supply is not necessary and VDDAU is therefore connected to the same switched power supply (3.3Vsw) as VDDA as illustrated in Figure 6-5.
When a continuous 3.3V supply is used to implement a low power sleep state, the VDDA supply pin must never exceed the VDDAU supply pin by more than 0.5V. One approach to satisfying this power sequencing requirement is to connect a Schottky diode between the power supplies to prevent VDDA from exceeding VDDAU by more than a forward-biased voltage drop. The Schottky diode must be sized appropriately if used; the forward voltage drop must be less than 0.5V when the diode conducts current when VDDA exceeds VDDAU. See Figure 6-6 and Figure 6-8.
Proper decoupling of the LAN8670/1/2 power distribution network is a prerequisite for stable operation and best EMC performance. Low ESR 0.1 μF and 0.01 μF decoupling capacitors are placed at each power pin of the device for localized decoupling. These decoupling capacitors should be located as close as possible to the pin to minimize parasitic inductance and maximize their effectiveness. This is typically done by placing the decoupling capacitors on the opposite side of the board from the device directly under the pin and connecting them to the exposed pad. Priority is always given to the placement of the smaller 0.01 μF decoupling capacitor closer to the corresponding pin rather than the larger 0.1 μF capacitor. Each decoupling capacitor is ideally connected to the power plane through two vias to minimize interconnection inductance. Decoupling capacitors should not share vias.
In addition to the decoupling capacitors at each pin, a bulk capacitor, typically 10 μF, is placed near the LAN8670/1/2 in the direction of the power supply that will be supplying current. The bulk capacitors serve to provide low frequency energy that is outside the supply’s response time.
EMI sensitive applications requiring increased noise performance, may optionally add ferrite beads such as the Würth 742792640 to create localized power islands around the device for the VDDA, VDDAU, and VDDP supplies as illustrated in Figure 6-7 and Figure 6-8. When a ferrite bead is used, it should have a resistance of around 300Ω at 100 MHz. Additionally, the ferrite bead must have a DC current rating of at least twice the maximum supply current of the corresponding power pins to supply power and avoid core saturation and degradation in performance. During the prototype phase, it is recommended to include the option for adding ferrite beads should the need arise to improve noise immunity.
Depending on the properties of the ferrite bead, its combination with the small decoupling capacitors may cause resonant noise amplification at certain frequencies, leading to an undesired amplification of noise in the system and resulting in increased electromagnetic radiation and noise coupling in form of amplitude noise and jitter. Since the ferrite bead selection is highly dependent on the noise in the system, which varies from design to design, the large bulk capacitor, typically 10 μF, is recommended to be placed on the device side of the ferrite bead. When ferrite beads are used, a 10 μF bulk capacitor on the supply side of the ferrite bead is not necessary. See Figure 6-7 and Figure 6-8.
Ideally, the board stackup will contain a large power plane layer next to a ground plane layer. The capacitance between the power and ground planes serve to provide high frequency, low inductance decoupling. When local power islands are used, the islands should be smaller planes underneath the LAN8670/1/2, again adjacent to a ground plane to provide high-frequency capacitive decoupling. The use of power tracks is discouraged but, if used, should be as short and wide as possible to minimize sheet resistance and current dependent voltage ripple at the power distribution to the pins.
The exposed ground pad (ePAD) of the package serves as the primary ground connection of the device and must be adequately connected to the PCB ground plane through an array of vias as specified in the Packaging Information section.
The analog pins (WAKE_IN, TRXP, TRXN, XTI/REFCLKIN, and XTO) pins must never be driven to more than the VDDAU supply. Furthermore, all other digital pins must never be driven to more than the VDDP supply. These requirements are applicable during power-up and power-down, as well as during normal operating conditions.
