6.7 Crystal Oscillator Selection

Oscillator margin is a measure of the stability of an oscillator circuit, and is defined in Equation 6-1 as the ratio of the oscillator’s negative resistance (R_NEG) to the crystal’s ESR (R_ESR).

$\mathrm{Margin}=\frac{\left|R_{\mathrm{NEG}}\right|}{R_{\mathrm{ESR}}}=\frac{\left|R_{\mathrm{VAR}}\right|+R_{\mathrm{ESR}}}{R_{\mathrm{ESR}}}$

The negative resistance can be measured by placing a variable resistor (R_VAR) in series with the crystal and finding the largest resistor value where the crystal still starts up properly. This point would be just below where the oscillator does not start-up or where the start-up time is excessively long. Ideally, oscillator margin should be greater than 10, and should be at least 5. Smaller oscillator margin can affect the ability of the oscillator to start up.

The load capacitance, C_L, which is specified when ordering the crystal, is calculated from the capacitance on each leg of the crystal, C_x, combined with the stray capacitance, C_stray, which is contributed by PCB traces and chip pins. C_strayis usually in the range of 2 pF to 5 pF. The clock circuit requires that both crystal pins have matching C_x. C_L can then be calculated from

$C_L=\frac{1}{2}{C}_x+C_{stray}$

Larger capacitors also have a negative effect on oscillator margin. It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (XTI/XTO). The transconductance gain (g_m) of the internal inverting amplifier is nominally 18.2 mS.

The crystal cut and tolerance value listed in the Crystal Specifications section are typical values and may be changed to suit differing system requirements. Higher ESR values (than those listed in Crystal Specifications) run the risk of having start-up problems and should be thoroughly tested before being used. Contact the crystal manufacturer for more information.