28.3.4 Sleep Mode Operation

Writing the Run In Standby (RUNSTDBY) bit in the Control A (CCL.CTRLA) register to ‘1’ will allow the system clock to be enabled in Standby sleep mode.

If RUNSTDBY is ‘0’, the system clock will be disabled in Standby sleep mode. If the Filter, edge detector, or Sequential logic is enabled, the LUT output will be forced to ‘0’ in Standby sleep mode. In Idle sleep mode, the truth table decoder will continue operation, and the LUT output will be refreshed accordingly, regardless of the RUNSTDBY bit.

If the Clock Source (CLKSRC) bit in the LUT n Control A (CCL.LUTnCTRLA) register is written to ‘1’, the LUT input 2 (IN[2]) will always clock the Filter, edge detector, and Sequential block. The availability of the IN[2] clock in sleep modes will depend on the sleep settings of the peripheral employed.