22.5.5 Control E
| Name: | CTRLE |
| Offset: | 0x04 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DISEOC | SCAPTUREB | SCAPTUREA | RESTART | SYNC | SYNCEOC | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – DISEOC Disable at End of TCD Cycle Strobe
When this bit is written to ‘1’, the TCD will
automatically disable at the end of the TCD cycle.
Note that ENRDY in TCDn.STATUS will stay low until the TCD is disabled.
Writing to this bit has effect only if there is no ongoing synchronization of the ENABLE value in TCDn.CTRLA with the TCD domain. See also the ENRDY bit in TCDn.STATUS.
Bit 4 – SCAPTUREB Software Capture B Strobe
When this bit is written to ‘1’, a software capture
to the Capture B (TCDn.CAPTUREBL/H) register is triggered as soon as
synchronization to the TCD clock domain occurs.
Writing to this bit has effect only if there is no ongoing synchronization of a command. See also the CMDRDY bit in TCDn.STATUS.
Bit 3 – SCAPTUREA Software Capture A Strobe
When this bit is written to ‘1’, a software capture
to the Capture A (TCDn.CAPTUREAL/H) register is triggered as soon as
synchronization to the TCD clock domain occurs.
Writing to this bit has effect only if there is no ongoing synchronization of a command. See also the CMDRDY bit in TCDn.STATUS.
Bit 2 – RESTART Restart Strobe
When this bit is written to ‘1’, a restart of the
TCD counter is executed as soon as this bit is synchronized to the TCD
domain.
Writing to this bit has effect only if there is no ongoing synchronization of a command. See also the CMDRDY bit in TCDn.STATUS.
Bit 1 – SYNC Synchronize Strobe
When this bit is written to ‘1’, the
double-buffered registers will be loaded to the TCD domain as soon as this bit
is synchronized to the TCD domain.
Writing to this bit has effect only if there is no ongoing synchronization of a command. See also the CMDRDY bit in TCDn.STATUS.
Bit 0 – SYNCEOC Synchronize End of TCD Cycle Strobe
When this bit is written to ‘1’, the
double-buffered registers will be loaded to the TCD domain at the end of the
next TCD cycle.
Writing to this bit has effect only if there is no ongoing synchronization of a command. See also the CMDRDY bit in TCDn.STATUS.