1.4.1 Power-up/down Sequence (ATWINC/ATWILC)

The power-up/down sequence for ATWINC/ATWILC is shown in the following figure. The timing parameters are provided in following the table.

Figure 1-5. Power-up/down Sequence (ATWINC/ATWILC)

Table 1-2. Power-up/down Sequence Timing Parameters
Parameter	Min.	Units	Description
t_A	0	ms	VBATT rise to VDDIO rise VBATT and VDDIO can rise simultaneously or can be tied together. VDDIO must not rise before VBATT.
t_B	0	ms	VDDIO rise to CHIP_EN rise CHIP_EN must not rise before VDDIO. CHIP_EN must be driven high or low, not left floating.
t_C	5	ms	CHIP_EN rise to RESETN rise This delay is needed because the XO clock must stabilize before RESETN removal. RESETN must be driven high or low, not left floating.
t_A’	0	ms	VDDIO fall to VBATT fall VBATT and VDDIO can fall simultaneously or can be tied together. VBATT must not fall before VDDIO.
t_B’	0	ms	CHIP_EN fall to VDDIO fall VDDIO must not fall before CHIP_EN. CHIP_EN and RESETN can fall simultaneously.
t_C’	0	ms	RESETN fall to VDDIO fall VDDIO must not fall before RESETN. RESETN and CHIP_EN can fall simultaneously.

It is mandatory that the ATWINC/ATWILC chip is in the right bootloader state for establishing connection from GUI through I2C. To do that, the host MCU must power-up the ATWINC/ATWILC chip and then perform the reset sequence as defined in the figure Power-up/down Sequence (ATWINC/ATWILC). This is done very easily from the host MCU by calling the nm_bsp_init() and nm_bsp_reset() function. The code snippet for the same is as shown below,

int main(void)
{/* Initialize the board. */
system_init();
/* Initialize the BSP. */
nm_bsp_init();
nm_bsp_reset();
while(1) {
}
}