4.1.1.2 Device Response Upon Reset or Power-Up

Upon powering up the device or resetting it by holding the SI/O line low for t_RESET or t_DSCHG, the host must release the line, which will be pulled high by an external pull-up resistor. The host must then wait an additional minimum time of t_RRT before requesting a Discovery Response Acknowledge from the device.

The Discovery Response Acknowledge sequence begins when the host drives the SI/O line low, which will start the AT21CS01/AT21CS11 internal timing circuits. The host must continue to drive the line low for t_DRR.

During the t_DRR time, the AT21CS01/AT21CS11 will respond by concurrently driving SI/O low. The device will continue to drive SI/O low for a total time of t_DACK. The host should sample the state of the SI/O line at t_MSDR past the initiation of t_DRR. By definition, the t_DACK minimum is longer than the t_MSDR maximum time, thereby ensuring the host can always correctly sample the SI/O for a level less than V_IL. After the t_DACK time has elapsed, the AT21CS01/AT21CS11 will release SI/O, which will be pulled high by the external pull‑up resistor.

The host must then wait t_HTSS to create a Start condition before continuing with the first command (see Start/Stop Condition for more details about Start conditions). By default, the device will exit Reset in High-Speed mode. Changing the device to Standard Speed mode is covered in Standard Speed Mode (Opcode Dh).

The timing requirements for the Reset and Discovery Response sequence for both Standard Speed and High-Speed mode can be found in AT21CS01/AT21CS11 AC Characteristics.