3.1 Start-up Configuration

The MCP16701’s turn-on (start-up) sequence (see Figure 3-2) is typically initiated by a logic HIGH transition on the EN pin. If EN is connected to VIN, the sequence will begin when VIN exceeds the AVCC and VDD undervoltage lockout (UVLO) thresholds. The device also features a configurable debounce delay for both the rising and falling edges of the EN signal, ensuring reliable and noise-immune start-up.

The MCP16701 supports four sequence steps, each with up to sixteen programmable delays, enabling up to 64 unique power channel activation instances (4 steps × 16 delays). If a specific output voltage must be fully established before another is enabled, these outputs should be assigned to different sequence steps, as defined by the ONSEQ[1:0] bits. The next sequence step is only initiated once all power channels in the current step are fully established.

For applications with strict sequencing and voltage level requirements—such as the VDD1 and VDD2/VDDQ rails for LPDDR2/3/4 memory—it is recommended to assign these rails to separate sequence steps. This ensures that if the first channel fails to start, subsequent channels will not attempt to power up, maintaining compliance with JEDEC power supply ramping specifications.

When multiple channels are assigned to the same sequence step, their start-up times are determined solely by the programmed turn-on delay (ONDLY[3:0] bits), allowing independent initiation within that step.