3.3 Soft Start Ramp and Dynamic Voltage Scaling (DVS) Configuration

The soft start rate controls how quickly the supply voltage ramps to its nominal level during start-up, while Dynamic Voltage Scaling (DVS) allows for real-time adjustment of the supply voltage to optimize power consumption, thermal performance and efficiency based on workload demands.

The MCP16701 provides a configurable soft start ramp, ensuring controlled and monotonic voltage transitions. Buck and LDO output voltages feature non-uniform step sizes (12.5 mV or 25 mV). When dynamically adjusting the output voltage between these regions, the device maintains a consistent average ramp rate by updating at 12.5 mV/step or 25 mV/step as appropriate, with twice the update rate in the 12.5 mV region. This approach ensures smooth transitions during both soft start and DVS events.

The soft start rate is programmable via the ONSR[2:0] bits, while the DVS rate is set using the DVSSR[1:0] bits, applicable to both positive and negative DVS transitions.

Figure 3-4 illustrates the above-mentioned concepts.

These features enable designers to maintain a consistent ramp rate, reliably estimate output voltage changes, and protect the FPGA from inrush current and voltage overshoot. Additionally, they support optimized power efficiency and thermal management, reducing power consumption during low activity states while allowing for performance boosts as needed.