15.6.10 Peripheral Write Protection Status B
Reading the STATUSB register returns the peripheral write protection status of the indicated peripherals:
0 Peripheral is not write protected.
1 Peripheral is write protected.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUSB |
| Offset: | 0x38 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TRNG | SQI1 | SQI0 | GMAC | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CAN5 | CAN4 | CAN3 | CAN2 | CAN1 | CAN0 | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SPI_IXS1 | SPI_IXS0 | PTC | AC | ADC | TCC9 | TCC8 | TCC7 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TCC6 | TCC5 | TCC4 | TCC3 | TCC2 | TCC1 | TCC0 | SERCOM9 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 27 – TRNG Peripheral TRNG Write Protection Status
Bits 25, 26 – SQIx Peripheral SQIx Write Protection Status, x = 0,1
For SQI1 see Note 2.
Bit 24 – GMAC Peripheral GMAC Write Protection Status
Bits 16, 17, 18, 19, 20, 21 – CANx Write Protection Status, x = 0,1,..5
For CAN4 and CAN5 see Note 2.
For CAN2 and CAN3 see Note 1.
Bits 14, 15 – SPI_IXS Peripheral SPI Write Protection Status
Bit 13 – PTC Peripheral PTC Write Protection Status
Bit 12 – AC Peripheral AC Write Protection Status
Bit 11 – ADC Peripheral ADC Write Protection Status
Bits 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 – TCCx Peripheral TCC Write Protection Status, x = 0,1,...9
Bit 0 – SERCOM9 Peripheral SERCOM Write Protection Status
See Note 3.