29.7.5 Event Control
Note: This register is write protected and can only be written when CTRLA.ENABLE =
0.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
Important: On devices with security attribution
Non-Secure accesses, read and write accesses (RW*) are allowed only if the external
interrupt x (EXTINTx) is set as Non-Secure in the NONSEC register (NONSEC.EXTINTx
bit). Some restrictions apply for the Non-Secure accesses to an Enabled-Protected
register as it will not be possible for the Non-Secure to configure it once this
register is enabled by the Secure application. This will require some veneers to be
implemented on Secure side.
| Name: | EVCTRL |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EXTINTEO[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EXTINTEO[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – EXTINTEO[15:0] External Interrupt Event Output Enable
| Value | Description |
|---|---|
| 0 | Event from pin EIC_EXTINTx is disabled. |
| 1 | Event from pin EIC_EXTINTx is enabled and will be generated when EIC_EXTINTx pin matches the external interrupt sensing configuration. |