32.4 Signal Interface
The ETH Controller module includes the following signal interfaces:
- MII, RMII, and GMII to an external PHY
- MDIO interface for external PHY management
- Client APB interface for accessing GMAC registers
- Host AXI interface for memory access
- GTSUCOMP signal for TSU timer count value comparison
| Signal Name | Function | GMII | MII | RMII |
|---|---|---|---|---|
| GMAC_TXCK | Transmit Clock (25Mhz) | Not Used | Used | Not Used |
| GMAC_GREFCK | Reference Clock (50MHz) | Not Used | Not Used | Used |
| GMAC_GTXCK | 125 MHz output Clock | Used | Not Used | Not Used |
| GMAC_GTXEN | Transmit Enable | Used | Used | Used |
| GMAC_GTX[7:0] | Transmit Data | [7:0] | [3:0] | [1:0] |
| GMAC_GRX[7:0] | Receive Data | [7:0] | [3:0] | [1:0] |
| GMAC_GTXER | Transmit Coding Error | Used | Used | Not Used |
| GMAC_GRXER | Receiving Coding Error | Used | Used | Used |
| GMAC_GRXCK | Receive Clock | Used | Used | Not Used |
| GMAC_GRXDV | Receive Data Valid | Used | Used | Not Used |
| GMAC_GCRS | Carrier Sense | Used | Used | Not Used |
| GMAC_GCRS_DV | Carrier Sense and Data Valid | Not Used | Not Used | Used |
| GMAC_GCOL | Collision Detect | Used | Used | Not Used |
| GMAC_GMDC | Management Data Clock | Used | Used | Used |
| GMAC_GMDIO | Management Data Input/Output | Used | Used | Used |