20.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers must be synchronized when written or read.

An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRLm.CHEN). When changing this bit, the bit value must be read-back to ensure the synchronization is complete and to assert glitch free internal operation. Changing the bit value under ongoing synchronization will not generate an error.

The following registers are synchronized when written:
  • The Generic Clock Generator Control register (GENCTRLn)
  • The Control A register (CTRLA)

Required write synchronization is denoted by the “Write Synchronized” property in the register description.

Important: To facilitate the use of sleep modes, the following conditions must be met:
  1. PLL0 must be dedicated to the CPU.
  2. PLL0 must be stepped down in <= 75 MHz increments to <= 75 MHz output when entering sleep modes.
  3. PLL0 must be stepped up to the operating frequency in <= 75 MHz increments after exiting Sleep Modes.
  4. The step delay for both of these processes needs to be >= 1 us.