20.7 Register Summary
For descriptions and definitions of both Register and bitfield properties, refer to Register Properties.
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | CTRLA | 7:0 | SWRST | |||||||
0x01 ... 0x03 | Reserved | |||||||||
| 0x04 | SYNCBUSY | 31:24 | ||||||||
| 23:16 | GENCTRL15 | GENCTRL14 | ||||||||
| 15:8 | GENCTRL13 | GENCTRL12 | GENCTRL11 | GENCTRL10 | GENCTRL9 | GENCTRL8 | GENCTRL7 | GENCTRL6 | ||
| 7:0 | GENCTRL5 | GENCTRL4 | GENCTRL3 | GENCTRL2 | GENCTRL1 | GENCTRL0 | SWRST | |||
0x08 ... 0x1F | Reserved | |||||||||
| 0x20 | GENCTRL0 | 31:24 | DIV[15:8] | |||||||
| 23:16 | DIV[7:0] | |||||||||
| 15:8 | RUNSTDBY | DIVSEL | OE | OOV | IDC | GENEN | ||||
| 7:0 | SRC[4:0] | |||||||||
| ... | ||||||||||
| 0x5C | GENCTRL15 | 31:24 | DIV[15:8] | |||||||
| 23:16 | DIV[7:0] | |||||||||
| 15:8 | RUNSTDBY | DIVSEL | OE | OOV | IDC | GENEN | ||||
| 7:0 | SRC[4:0] | |||||||||
0x60 ... 0x7F | Reserved | |||||||||
| 0x80 | PCHCTRL0 | 31:24 | ||||||||
| 23:16 | ||||||||||
| 15:8 | ||||||||||
| 7:0 | WRTLOCK | CHEN | GEN[3:0] | |||||||
| ... | ||||||||||
| 0x017C | PCHCTRL63 | 31:24 | ||||||||
| 23:16 | ||||||||||
| 15:8 | ||||||||||
| 7:0 | WRTLOCK | CHEN | GEN[3:0] | |||||||