45.5.2.4 Enabling, Disabling and Resetting

The TRAM is enabled by writing a ‘1’ to the Enable bit in the Control A register CTRLA.ENABLE bit (CTRLA<1>). The TRAM is disabled by writing a ‘0’ to CTRLA.ENABLE bit (CTRLA<1>).

The TRAM is reset by writing a ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST bit (CTRLA <0>)). All registers in the TRAM will be reset to their initial state, and the TRAM will be disabled. All data in the security RAM will be cleared to ‘0’.